Tag Archives: ZeBu-Server

Arteris and EVE Design Flow for System-on-Chip Development

Arteris and EVE teamed together on an integrated solution for system-on-chip (SoC) developers. The design flow enables engineers to generate and use actual SoC register transfer level (RTL) implementations on EVE’s ZeBu-Server emulation platform. The integration flow helps SoC developers create and ship products sooner.

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EVE Adds Multi-User Capability to ZeBu-Server

ZeBu-Server, from EVE (Emulation & Verification Engineering), now offers superior multi-user capabilities that can support up to 25 users concurrently. Each ZeBu-Server user or design can utilize any of the available resources, and allocation of the emulation resources is completely automatic. Each user can have a dedicated host PC with its own PCIe interface for maximum bandwidth and PC computing power. The multi-user capability enables engineers to fully utilize hardware-assisted verification throughout the project cycle.

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EVE ZeBu-Server Features Smart Debug

The new ZeBu-Server comes standard with a powerful debug environment. ZeBu-Server features a wide array of tools that enables debugging at multiple levels of abstraction, because debugging a complex failure in a system-on-chip (SoC) design requires deterministically re-executing billions of clock cycles repeatedly until the problem is identified. ZeBu-Server is a scalable emulation system capable of handling up to one-billion application specific integrated circuit (ASIC) gates.

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