XJTAG will hold a free boundary scan training workshop at the UK’s Manufacturing Technology Centre (MTC). The workshop will provide an introduction to boundary scan and to show how the debug, test and programming process can be used throughout the product life cycle. The XJTAG workshop will take place Wednesday, June 12, 2013 in Coventry.
The SOI Industry Consortium, CEA-Leti and Soitec are organizing a workshop on fully depleted silicon-on-insulator (FD-SOI) technology for advanced semiconductor architectures. The forum, which includes technical presentations and discussions, will take place in San Francisco, California on February 24, 2012. The event provides semiconductor IC designers and manufacturers with the latest information and insights on using FD-SOI wafers to produce more power efficient ICs at the performance required for applications in mobile and consumer electronics.
The Silicon Integration Initiative will co-locate their OpenAccess Scripting Language Workshop at the Design Automation Conference. The Si2 workshop will be will be held on June 6, from 1:00 pm – 4:30 pm in Room 29AB in the San Diego Convention Center. Si2 is offering the OpenAccess Scripting Language Workshop free of charge. The DAC workshop is intended for chip design engineers who want to interact with OpenAccess programs or data in scripting languages (such as Tcl, Perl, Python, Ruby), either integrated with native C++ code or as stand-alone programs.
The 2011 International Symposium on Quality Electronic Design (ISQED) features seven keynote speeches, poster sessions, nine tutorials, over 100 technical presentations, and exhibits. The conference will take place March 14-16 at the Hyatt Regency Hotel in Santa Clara, CA. The event is co-located with Sematech’s Design for Reliability Workshop (Stress Management for 3D ICs Using Through Silicon Vias) and the International Electronic Design Education Conference (IEDEC). the ISQED keynote speeches and exhibits are free and open to all.
At DAC 2010, ECSI (Electronic Chips & Systems design Initiative) is offering a workshop titled, Choosing Advanced Verification Methods. The workshop will present a survey of recent verification solution advances and will bring insight into the effects these technologies are having on leading edge design projects. Measurable impact on quality, time-to-market, schedule, efficiency, and actual ROI will be analyzed. Participants will be able to hear from real engineers about their verification problems and their experiences in the deployment of these technologies.
Leti research center is hosting a workshop on innovative memory technologies at MINATEC during Minatec Crossroads ’10 events on Monday, June 21. The workshop will explore the latest achievements in semiconductor memory technologies. Topics will range from short-term to long-term memory solutions. The workshop is part of the 3rd Minatec Crossroads ’10 June 21-25. Leti, a CEA laboratory located in Grenoble, is one of the main European applied research centers in electronics.
The SAME 2010 Forum and the SAFA workshop have issued separate calls for papers. The SAME 2010 Forum provides a venue for discussions and technical knowledge sharing with the opportunity to meet industrials, high-tech companies displaying and demonstrating microelectronic related products. The SAFA’2010 Workshop focuses on techniques around formal analysis.
The OMG Real-time, Embedded and Enterprise-Scale Time-Critical Systems Workshop will be held on May 24-26, 2010 in Arlington, VA, USA. The embedded systems workshop provides a forum for software engineers and researchers to learn about new design approaches, share their experiences, and find out about emerging standards. An early-bird registration discount is available until Monday, April 19, 2010.
The 2010 SEMATECH Knowledge Series (SKS) conferences will focus on difficult questions in lithography, advanced technologies, manufacturing, and strategy. Included are a new set of meetings on installed-base equipment utilization, and a new interconnect workshop in stress management for 3D chips utilizing through-silicon vias (TSVs). All SKS meetings are open to the public.
Apache Design Solutions announced a workshop at DesignCon 2010 to facilitate industry-wide discussion on the challenges, methodologies, and techniques required for chip-package-systems (CPS) convergence. The workshop, entitled “Practical Methodologies for Power/Signal Integrity of Chip-Package-Board Designs,” will be held from 9am to noon on Thursday, February 4th in the Santa Clara Convention Center.