Tanner EDA announced version 15 of the HiPer Silicon design suite. HiPer Silicon v15 gives designers a complete analog design flow from schematic capture, circuit simulation, and waveform probing to physical layout and verification. HiPer Silicon v15 full-flow design suite is available now for the Windows operating system. A Linux version will be available later.
SynaptiCAD’s Gates-on-the-Fly (GOF) Verilog netlist editor and incremental schematic viewer now features schematic back annotation and waveform viewer cross-probing. Using one of SynaptiCAD’s waveform viewers, designers can view waveforms from a simulation (e.g. a VCD file) or a logic analyzer and show specific logic states annotated on GOF schematic windows. The schematic and the waveform displays are linked so that engineers can quickly control the simulation time that is displayed from either the schematic or the waveform windows.