Mentor Graphics introduced hardware and software solutions to accelerate the verification of High-Definition Multimedia Interface (HDMI) version 2.0 products. Mentor verification solutions enable designers to test the HDMI 2.0 devices integrated on their System-on-Chip (SoC) designs, and develop and stress-test their software and hardware with billions of verification cycles before silicon is available. The solutions are available for deployment at customer sites effective immediately.
Cadence Design Systems has developed the industry’s first verification IP that supports the new HDMI 2.0 specification. The HDMI 2.0 VIP enables a small verification team to deliver reliable results within very tight schedule constraints. By reducing the effort required to develop a verification solution, engineers can focus on other tasks crucial to project completion.
Mentor Graphics introduced iSolve SAS and SAS transaction-based verification IP (VIP) solution. iSolve SAS is a plug-and-play hardware interface to the Veloce family of hardware emulators. The VIP solution delivers both a simulation environment, using the Questa verification platform, and accelerated simulation environment using the Veloce hardware for the verification of SAS Gen2-compliant devices. Both solutions are available now for deployment at customer sites.
Cadence Design Systems announced a new Mobile PCI Express design IP (IP) and verification IP (VIP) solution. According to Cadence, the solution is the first IP and VIP to support the new M-PCIe specification. Mobile PCI Express enables engineers to develop products with both PC-class performance and extended battery life.
Cadence Design Systems introduced the industry’s first Automotive Ethernet Design IP and Verification IP (VIP) for the latest Automotive Ethernet Controllers. The new IP and VIP offering helps engineer to easily implement the latest automotive requirements and create advanced Ethernet-based products for in-vehicle communication. Cadence’s Design and Verification IP enables the development of Ethernet-based products for in-vehicle communication.
Cadence Design Systems has added new capabilities in their PCI Express Verification IP. The Cadence PCIe VIP now offers more in-depth verification of the most current PCI Express specification at both the block and system-on-chip (SoC) levels. The Cadence PCIe VIP is a broad, highly differentiated, and proven solution with distinct advantages for PCI Express verification. Cadence’s VIP solution includes over 40 interface protocols and more than 6,000 memory models that have been deployed in thousands of designs.
Mentor Graphics’ Questa Verification IP (VIP) now supports several MIPI Alliance specifications. This includes CSI, DSI and the recently announced LLI. Questa VIP is a comprehensive solution for SystemVerilog OVM and UVM test benches. Questa VIP support for MIPI protocols is available now for select customers.
Cadence Design Systems will be demonstrating their high-speed interface and memory IP solutions, and verification IP at the 2011 Intel Developer Forum. The demonstrations will take place in the Cadence Booth #422. The Intel Developer Forum will be held September 13-15 at the Moscone Center in San Francisco, California.
SystemVerilog-based and Open Verification Methodology (OVM)-compliant PCI Express Gen3 verification IP (Genie-PCIe3 VIP) is now available from Perfectus Technology. Genie-PCIe3 VIP helps designers accelerate the verification of PCI Express Gen3-based products. Genie-PCIe3 features a complete set of intelligent verification components for verifying PCI Express 1.1/2.0/3.0 and SR-IOV-based designs and it works in any verification environment, including SystemVerilog and OVM methodology. PCIe Gen3 VIP is available immediately.