Tag Archives: VHDL

Mentor Graphics Debuts Questa, Veloce ARM AMBA 5 CHI and AMBA 4 ACE Tools

Mentor Graphics has added cache coherent interconnect subsystem verification to the Questa and Veloce platforms. ARM AMBA 5 CHI and AMBA 4 ACE specifications enable high performance, coherent SoC design functionality to be at the heart of the Questa and Veloce platforms. The Questa and Veloce platform AMBA 4 ACE verification solutions are available now. The AMBA 5 CHI verification solutions are available to approved ARM AMBA 5 CHI licensees.

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OneSpin Solutions Debuts RTL-to-RTL Equivalence Checking Software

OneSpin Solutions launched 360 EC-RTL equivalence checking software. OneSpin’s 360 EC-RTL compares revisions of register transfer level (RTL) code. 360 EC-RTL is part of the OneSpin 360 EC Product Family. It is a RTL-to-RTL equivalence checker used to exhaustively compare two revisions of synthesizable RTL code. The software features robust register, sequential and power optimization verification. 360 EC-RTL is shipping now.

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SynaptiCAD Verilog2VHDL Tool Now Supports Verilog 2005

SynaptiCAD Verilog2VHDL tool

SynaptiCAD rolled out a new version of their Verilog2VHDL tool. The SynaptiCAD V2V tools translate bidirectionally between Verilog and VHDL source code. The translators are are ideal for converting behavioral and/or RTL-level code to a preferred design language. The V2V translation software is available on Windows and Linux. The SynaptiCAD software can be licensed on either a permanent or leased basis, and both floating and node-locked versions are available.

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SynaptiCAD V2V Translators Feature Verilog 2001 Support, Graphical Debugger

SynaptiCAD rolled out a new version of their V2V translator software. The SynaptiCAD V2V tools translate between VHDL and Verilog source code that supports Verilog 2001 code constructs. SynaptiCAD also announced that their BugHunter Pro can now be used as a graphical debugging environment for translating and testing the new models.

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Sigasi 2.0 Starter Edition for Free

Sigasi is releasing a free Starters Edition of their Sigasi HDT design entry and code comprehension tool. The starters edition was designed to replace traditional text editors like Vi and Emacs. Sigasi 2.0 Starters Edition will be permanently available free of charge. The second generation of their IDE tool for the VHDL language has been in public beta for three months.

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VHDL-AMS Modeling Techniques Workshop

Dolphin Integration is offering a VHDL-AMS modeling training workshop in April. The VHDL-AMS Modeling training event will present the language constructs of either Verilog-AMS or VHDL-AMS. It covers techniques for creating and validating behavioral models. Designers will learn how to perform bottom-up modeling through structural assembly of behavioral models for multi-level simulations. The seminar is ideal for designers involved in mixed-signal electrical designs and/or analog behavioral modeling and simulation.

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New Version of SynaptiCAD TestBencher Pro

SynaptiCAD rolled out a new verion of TestBencher Pro, which is a VHDL and Verilog system-level testbench generation software. The tool simplifies the process of creating and applying random bus transactions to RTL and gate-level models. The latest version of TestBencher Pro simplifies the creation of testbenches that reside in a different compiled library from the design being tested.

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SynaptiCAD BugHunter Pro VHDL and Verilog Testbench, Debugging Tool

SynaptiCAD rolled out the latest version of BugHunter Pro, which is a VHDL and Verilog testbench generation and debugging tool. The updated version of BugHunter Pro supports 64-bit versions of Mentor Graphics ModelSim and Cadence Incisive simulators. A node-locked license for BugHunter sells for $2500 on Windows. Floating licenses sell for $5000 on Windows and $6000 on Unix. A node locked copy of the WaveFormer/BugHunter product bundle sells for $4000 on Windows.

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