Mentor Graphics has added cache coherent interconnect subsystem verification to the Questa and Veloce platforms. ARM AMBA 5 CHI and AMBA 4 ACE specifications enable high performance, coherent SoC design functionality to be at the heart of the Questa and Veloce platforms. The Questa and Veloce platform AMBA 4 ACE verification solutions are available now. The AMBA 5 CHI verification solutions are available to approved ARM AMBA 5 CHI licensees.
OneSpin Solutions launched 360 EC-RTL equivalence checking software. OneSpin’s 360 EC-RTL compares revisions of register transfer level (RTL) code. 360 EC-RTL is part of the OneSpin 360 EC Product Family. It is a RTL-to-RTL equivalence checker used to exhaustively compare two revisions of synthesizable RTL code. The software features robust register, sequential and power optimization verification. 360 EC-RTL is shipping now.
SynaptiCAD rolled out a new version of their Verilog2VHDL tool. The SynaptiCAD V2V tools translate bidirectionally between Verilog and VHDL source code. The translators are are ideal for converting behavioral and/or RTL-level code to a preferred design language. The V2V translation software is available on Windows and Linux. The SynaptiCAD software can be licensed on either a permanent or leased basis, and both floating and node-locked versions are available.
SynaptiCAD rolled out a new version of their V2V translator software. The SynaptiCAD V2V tools translate between VHDL and Verilog source code that supports Verilog 2001 code constructs. SynaptiCAD also announced that their BugHunter Pro can now be used as a graphical debugging environment for translating and testing the new models.
Synopsys introduced their CustomExplorer Ultra mixed-signal verification environment. CustomExplorer Ultra is a comprehensive regression and analysis environment. It increases verification productivity and streamlines the verification process for analog and mixed-signal designs. Synopsys CustomExplorer Ultra is part of their Discovery Verification Platform. The CustomExplorer Ultra mixed-signal verification environment is available now.
Dolphin Integration is offering a VHDL-AMS modeling training workshop in April. The VHDL-AMS Modeling training event will present the language constructs of either Verilog-AMS or VHDL-AMS. It covers techniques for creating and validating behavioral models. Designers will learn how to perform bottom-up modeling through structural assembly of behavioral models for multi-level simulations. The seminar is ideal for designers involved in mixed-signal electrical designs and/or analog behavioral modeling and simulation.
SynaptiCAD rolled out a new verion of TestBencher Pro, which is a VHDL and Verilog system-level testbench generation software. The tool simplifies the process of creating and applying random bus transactions to RTL and gate-level models. The latest version of TestBencher Pro simplifies the creation of testbenches that reside in a different compiled library from the design being tested.
SynaptiCAD rolled out the latest version of BugHunter Pro, which is a VHDL and Verilog testbench generation and debugging tool. The updated version of BugHunter Pro supports 64-bit versions of Mentor Graphics ModelSim and Cadence Incisive simulators. A node-locked license for BugHunter sells for $2500 on Windows. Floating licenses sell for $5000 on Windows and $6000 on Unix. A node locked copy of the WaveFormer/BugHunter product bundle sells for $4000 on Windows.
SynaptiCAD recently published a white paper that describes how their updated Gates-on-the-Fly (GOF) was used to find and fix failures identified by Cadence’s Conformal tool. SynaptiCAD’s Verilog netlist editor was updated to support easy correction of logic equivalence failures introduced during modifications to post-synthesis netlists, using equivalence check reports from either Cadence’s Conformal LEC or Synopsys’s Formality. Gates-on-the-Fly graphically analyzes and edits large Verilog netlists that have been generated from a synthesis or layout tool.
Real Intent launched Ascent Lint Version 1.2 for early functional verification. Ascent Lint v1.2 performs syntax and semantic Lint checks for complex SoC designs. Ascent Lint now offers rules from STARC Policy, Verilog and SystemVerilog Gotchas, Reuse Methodology Manual (RMM), Principles of Verifiable RTL Designs, and rules based on Real Intent industry expertise.