Tag Archives: verification

Jasper User Group to Take Place Next Month

Jasper User Group Meeting 2012

Jasper Design Automation will hold their annual user meeting November 12 -13, 2012. The Jasper User Group will gather designers, verification engineers and engineering managers from around the world to share the latest verification best practices. The event will take place at the Cypress Hotel in Cupertino, California.

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Cadence Incisive Debug Analyzer Reduces Debug Time by 40%

Cadence Design Systems launched the Incisive Debug Analyzer. The new tool is a verification debug solution for RTL, testbench and SoC verification. It helps designers reduce debug time and effort. The Incisive Debug Analyzer integrates seamlessly into existing Incisive debug flows, fully leveraging SimVision for waveform and transaction-level debug. The tool will be released at the end of the year.

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Cadence Design Systems Debuts Allegro v16.6 Printed Circuit Board

Cadence Design Systems ~ Allegro printed circuit board tool suite

Cadence Design Systems launched version 16.6 of their Allegro printed circuit board technology. The PCB tool is the first electrical CAD (ECAD) team collaboration environment for PCB design using Microsoft SharePoint technology. Cadence Allegro, integrated with SharePoint, improves team collaboration, design creation and control, and significant productivity improvements. Allegro v16.6 will be available in the fourth quarter of this year.

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Cadence Design Systems Publishes Mixed-Signal Methodology Guide

Mixed-Signal Methodology Guide ~ Cadence Design Systems

Cadence Design Systems announced a new publication: Mixed-Signal Methodology Guide. The design methodology book provides an overview of the design, verification and implementation methodologies required for advanced mixed-signal designs. The book addresses the complex problems facing the mixed-signal design community. It features mixed-signal design experts from Boeing, Cadence, ClioSoft and Qualcomm. The Mixed-Signal Methodology Guide is intended for chip designers and CAD engineers.

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2013 Design and Verification Conference Issues Call for Papers

Accellera Systems Initiative has issued a call for papers for the 2013 Design and Verification Conference. The deadline to submit an extended abstract (800 to 1,000 words) is August 21st. DVCon is a conference for the application of languages, tools and methodologies for the design and verification of electron systems and integrated circuits. DVCon 2013 will take place February 25-28, 2012 at the DoubleTree Hotel in San Jose, California.

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Synopsys Introduces IC Compiler 2012.06

Synopsys introduced version 2012.06 of their IC Compiler software. The latest release of IC Compiler release includes multiple advances to support giga-performance design. IC Compiler 2012.06 helps IC designers achieve higher clock frequencies more efficiently. Synopsys’ IC Compiler 2012.06 features optimizations that can boost operating clock speeds, expanded support for highly fragmented floorplans and new technologies that address advanced process effects.

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Cadence PCI Express Verification IP Supports PCIe PIPE4 Specification

Cadence Design Systems has added new capabilities in their PCI Express Verification IP. The Cadence PCIe VIP now offers more in-depth verification of the most current PCI Express specification at both the block and system-on-chip (SoC) levels. The Cadence PCIe VIP is a broad, highly differentiated, and proven solution with distinct advantages for PCI Express verification. Cadence’s VIP solution includes over 40 interface protocols and more than 6,000 memory models that have been deployed in thousands of designs.

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Synopsys DesignWare IP Available for SMIC 40-nanometer Low-Leakage Process

Synopsys DesignWare IP is now available on the SMIC 40-nanometer low-leakage (40LL) process. The DesignWare IP for the SMIC 40LL process includes USB 2.0 picoPHY, HDMI 1.4 TX PHY, DDR multiPHY, MIPI D-PHY, PCI Express 2.0/1.1 PHY, SATA 1.5Gb/s/3Gb/s PHY, SATA 6Gb/s PHY, and select audio codecs and data converter IP. DesignWare USB 3.0 PHY, HSIC PHY, data converters and AFE for LTE and Wi-Fi, and Embedded Memory and Logic Library IP are available for early adopters. Availability for the DesignWare HDMI RX PHY and DDR3/2 PHY IP is planned for Q4 2012.

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HiPer Simulation A/MS Features Tools from Tanner EDA, Aldec

Tanner EDA and Aldec teamed together on HiPer Simulation A/MS, which is an integrated co-simulation solution for analog and mixed-signal (A/MS) design. HiPer Simulation A/MS includes Tanner EDA’s T-Spice analog design capture and simulation tool, and Aldec’s Riviera-PRO mixed language digital simulator. The integrated solution helps both analog and digital designers to seamlessly resolve A/MS verification problems from one cohesive, integrated platform. HiPer Simulation A/MS is available on both Windows and Linux.

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Carbon Design Systems Launches Performance Analysis Kits

Carbon Performance Analysis Kits (CPAK) ~ Carbon Design Systems

Carbon Design Systems is accelerating the analysis, optimization and verification of system-on-chip (SoC) performance with their new Carbon Performance Analysis Kits (CPAK). The CPAK family for ARM Cortex processors includes reference hardware and software designs along with analysis and debug software for the Cortex-A9, Cortex-A15 and Cortex-A7 cores, and the ARM big.LITTLE subsystem. The CPAK Family for ARM Cortex A-Series Processors will be available in bare metal and Linux configurations in this quarter. Android configurations will be available in the second half of this year.

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