Mentor Graphics introduced hardware and software solutions to accelerate the verification of High-Definition Multimedia Interface (HDMI) version 2.0 products. Mentor verification solutions enable designers to test the HDMI 2.0 devices integrated on their System-on-Chip (SoC) designs, and develop and stress-test their software and hardware with billions of verification cycles before silicon is available. The solutions are available for deployment at customer sites effective immediately.
Cadence Design Systems announced the Palladium XP II Verification Computing Platform. The tool speeds up hardware and software verification by up to 50% and extends capacity to 2.3 billion gates. Palladium XP II Verification Computing Platform is part of an enhanced System Development Suite.
Cadence Design Systems introduced a new SpeedBridge Adapter for PCIe 3.0. The adapter provides easy bring-up and fast debug of PCIe-based designs when used with a Cadence Palladium Verification Computing Platform, and is backwards compatible with PCIe 2.0-, 1.1- and 1.0a-based designs. The Cadence SpeedBridge Adapter for PCIe 3.0 is available now.
Mentor Graphics has developed MIPI-protocol verification IP for their latest-generation Veloce hardware emulation platform. The Mentor MIPI VIP solution enables engineers to exhaustively stress test a device-under-test (DUT) that includes one or more MIPI protocol interfaces on their SoC, and run verification cycles at orders of magnitude faster than simulation.
Mentor Graphics introduced a comprehensive IP to System, UPF-based low-power verification flow. Mentor now has platform-level support of Unified Power Format in both the Questa functional verification platform and the Veloce family of hardware emulators that lets users create a single specification for power intent that is reusable and consistent, and facilitates low-power verification across simulation, formal and emulation.
Cadence Design Systems will hold their CDNLive Silicon Valley User Conference on March 12 and 13 in Santa Clara. CDNLive Silicon Valley brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems.
OneSpin Solutions launched 360 EC-RTL equivalence checking software. OneSpin’s 360 EC-RTL compares revisions of register transfer level (RTL) code. 360 EC-RTL is part of the OneSpin 360 EC Product Family. It is a RTL-to-RTL equivalence checker used to exhaustively compare two revisions of synthesizable RTL code. The software features robust register, sequential and power optimization verification. 360 EC-RTL is shipping now.
Mentor Graphics has made improvements to the Verification Academy. One of the new enhancements in the Verification Academy is the Coverage Cookbook. The Coverage Cookbook is a systematic methodology for developing functional coverage models and coverage-driven processes. The Mentor Verification Academy is a comprehensive resource for verification engineers, and provides access to information and online training on advanced functional verification technologies.
Synopsys has added a Performance Checker capability to their next-generation Discovery Verification IP (VIP) for the ARM AMBA 4 AXI4 protocol. The Performance Checker capability in the Synopsys Discovery VIP helps improve the productivity of engineering teams using the AMBA protocols to meet their SoC performance goals.
Breker Verification Systems launched a new verion of TrekSoC for SoC designs. The Breker software now supports multiple heterogeneous embedded processors. The new verification support for multiple heterogeneous processors helps project teams verify their SoCs more completely. The latest release of TrekSoC is available to qualified verification teams now. General availability is expected at the end of 2012.