Tag Archives: Verification IP

Mentor Graphics Questa Verification IP Supports MIPI Alliance Specifications

Mentor Graphics’ Questa Verification IP (VIP) now supports several MIPI Alliance specifications. This includes CSI, DSI and the recently announced LLI. Questa VIP is a comprehensive solution for SystemVerilog OVM and UVM test benches. Questa VIP support for MIPI protocols is available now for select customers.

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Synopsys Introduces Discovery Verification IP Family with VIPER Architecture

Synopsys introduced their Discovery Verification IP (VIP) family. Synopsys VIP is written entirely in SystemVerilog and is based on the new VIPER Architecture. It offers speeds and simplifies the verification of complex protocols and SoC designs. The Synopsys Discovery VIP family includes Protocol Analyzer, which is a unique prothonotary debug environment. Synopsys VIP is available for a variety of protocols, including USB 3.0, ARM AMBA AXI3, AXI4, ACE, HDMI, MIPI (CSI-2, DSI, HSI, etc.), Ethernet 40G/100G, PCI Express, SATA, and OCP.

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Cadence Takes Design and Verification IP to Intel Developer Forum

Cadence Design Systems will be demonstrating their high-speed interface and memory IP solutions, and verification IP at the 2011 Intel Developer Forum. The demonstrations will take place in the Cadence Booth #422. The Intel Developer Forum will be held September 13-15 at the Moscone Center in San Francisco, California.

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