Tag Archives: Verification IP

Mentor Graphics Debuts Emulation Tools for Verification of HDMI 2.0

Mentor Graphics introduced hardware and software solutions to accelerate the verification of High-Definition Multimedia Interface (HDMI) version 2.0 products. Mentor verification solutions enable designers to test the HDMI 2.0 devices integrated on their System-on-Chip (SoC) designs, and develop and stress-test their software and hardware with billions of verification cycles before silicon is available. The solutions are available for deployment at customer sites effective immediately.

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Cadence Develops First Verification IP for HDMI 2.0

Cadence Design Systems has developed the industry’s first verification IP that supports the new HDMI 2.0 specification. The HDMI 2.0 VIP enables a small verification team to deliver reliable results within very tight schedule constraints. By reducing the effort required to develop a verification solution, engineers can focus on other tasks crucial to project completion.

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New Cadence Verification IP Models Supports Latest Memory Standards

Cadence Design Systems released new verification IP (VIP) models for the latest memory standards: LPDDR4, Wide I/O 2, eMMC 5.0, HMC and DDR4 LRDIMM. LPDDR4 and Wide I/O 2 are key new standards for memory interfaces, and the availability of memory models will help designers to take advantage of the new standards quickly.

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Mentor Graphics Debuts MIPI Verification IP for Veloce Hardware Emulation

Mentor Graphics has developed MIPI-protocol verification IP for their latest-generation Veloce hardware emulation platform. The Mentor MIPI VIP solution enables engineers to exhaustively stress test a device-under-test (DUT) that includes one or more MIPI protocol interfaces on their SoC, and run verification cycles at orders of magnitude faster than simulation.

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Mentor Graphics Launches iSolve SAS and Verification IP Solutions

Mentor Graphics Veloce Emulation Systems

Mentor Graphics introduced iSolve SAS and SAS transaction-based verification IP (VIP) solution. iSolve SAS is a plug-and-play hardware interface to the Veloce family of hardware emulators. The VIP solution delivers both a simulation environment, using the Questa verification platform, and accelerated simulation environment using the Veloce hardware for the verification of SAS Gen2-compliant devices. Both solutions are available now for deployment at customer sites.

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Cadence Debuts Mobile PCI Express Design IP and Verification IP

Cadence Design Systems announced a new Mobile PCI Express design IP (IP) and verification IP (VIP) solution. According to Cadence, the solution is the first IP and VIP to support the new M-PCIe specification. Mobile PCI Express enables engineers to develop products with both PC-class performance and extended battery life.

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Cadence Design Systems Debuts Automotive Ethernet Design IP and Verification IP

Driving SoC Realization ~ Cadence Design Systems

Cadence Design Systems introduced the industry’s first Automotive Ethernet Design IP and Verification IP (VIP) for the latest Automotive Ethernet Controllers. The new IP and VIP offering helps engineer to easily implement the latest automotive requirements and create advanced Ethernet-based products for in-vehicle communication. Cadence’s Design and Verification IP enables the development of Ethernet-based products for in-vehicle communication.

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Avery Design Systems Introduces SCSI-Xactor Verification IP for PCIe-based SSD

Avery Design Systems recently introduced their SCSI-Xactor verification IP. SCSI-Xactor targets SCSI Express for high performance PCIe-based SSDs. Avery’s verification IP is a complete solution for SCSI Express core and system design. SCSI-Xactor helps design and verification engineers to quickly and extensively test the functionality of SCSI Express controller-based designs.

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Cadence PCI Express Verification IP Supports PCIe PIPE4 Specification

Cadence Design Systems has added new capabilities in their PCI Express Verification IP. The Cadence PCIe VIP now offers more in-depth verification of the most current PCI Express specification at both the block and system-on-chip (SoC) levels. The Cadence PCIe VIP is a broad, highly differentiated, and proven solution with distinct advantages for PCI Express verification. Cadence’s VIP solution includes over 40 interface protocols and more than 6,000 memory models that have been deployed in thousands of designs.

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Cadence TripleCheck IP Validator Simplifies and Automates IP Compliance Testing

Cadence TripleCheck IP Validator for Faster IP Compliance Testing

Cadence Design Systems introduced their TripleCheck IP Validator. The test suite supports all major logic simulators, and it provides a simulator-independent native SystemVerilog and/or e coverage database that supports both leading test bench languages. Cadence TripleCheck IP Validator is available now for PCIe Gen 3. Cadence has support for several additional protocols in development for release later this year.

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