Cadence Design Systems has developed the industry’s first verification IP that supports the new HDMI 2.0 specification. The HDMI 2.0 VIP enables a small verification team to deliver reliable results within very tight schedule constraints. By reducing the effort required to develop a verification solution, engineers can focus on other tasks crucial to project completion.
Mentor Graphics’ Questa Verification IP (VIP) now supports several MIPI Alliance specifications. This includes CSI, DSI and the recently announced LLI. Questa VIP is a comprehensive solution for SystemVerilog OVM and UVM test benches. Questa VIP support for MIPI protocols is available now for select customers.
Mentor Graphics rolled out version 10.1 of their Questa functional verification platform. The 10.1 release features increased simulation and verification performance, enhanced support of the Universal Verification Methodology (UVM), accelerated coverage closure, and low power verification with comprehensive Unified Power Format (UPF) support. Questa functional verification platform is a tightly integrated solution for the functional verification of complex System-on-Chip (SoC), ASIC and FPGA designs.
Synopsys introduced their Discovery Verification IP (VIP) family. Synopsys VIP is written entirely in SystemVerilog and is based on the new VIPER Architecture. It offers speeds and simplifies the verification of complex protocols and SoC designs. The Synopsys Discovery VIP family includes Protocol Analyzer, which is a unique prothonotary debug environment. Synopsys VIP is available for a variety of protocols, including USB 3.0, ARM AMBA AXI3, AXI4, ACE, HDMI, MIPI (CSI-2, DSI, HSI, etc.), Ethernet 40G/100G, PCI Express, SATA, and OCP.
Mentor Graphics is expanding support for the Universal Verification Methodology with UVM Express and UVM Connect. UVM Express is one way to progressively adopt UVM methodology. UVM Connect provides standard TLM 1.0 and TLM 2.0 connectivity between models written in SystemC and UVM SystemVerilog. UVM Express and UVM Connect functionality is available now. They can be downloaded from the Mentor Verification Academy. Verification Academy modules on using UVM (UVM Express and UVM Advanced), training material and online documentation are also available.
Cadence Design Systems introduced over 600 new capabilities to improve verification productivity for ASIC and FPGA designers. The capabilities, along with support for the Accellera Universal Verification Methodology (UVM), will expand the scope of metric-driven verification (MDV) to help engineers achieve faster, more comprehensive verification closure and Silicon Realization.
Aldec introduced Riviera-PRO 2010.06 RTL and gate-level simulator. Riviera-PRO 2010.06 supports the Open Verification Methodology (OVM) co-authored by Cadence (NASDAQ:CDNS) and the early release of the Universal Verification Methodology (UVM) from Accellera. OVM and UVM provide common building blocks and predefined mechanisms for building reusable and expandable test environments that take full advantage of SystemVerilog verification capabilities. Riviera-PRO 2010.06 verification platform is available now.