Tag Archives: Universal Verification Methodology

Cadence Develops First Verification IP for HDMI 2.0

Cadence Design Systems has developed the industry’s first verification IP that supports the new HDMI 2.0 specification. The HDMI 2.0 VIP enables a small verification team to deliver reliable results within very tight schedule constraints. By reducing the effort required to develop a verification solution, engineers can focus on other tasks crucial to project completion.

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UVM Connect 2.2 Supports Open Verification Methodology

Mentor Graphics Universal Verification Methodology Connect (UVM Connect)

Mentor Graphics has extended their Universal Verification Methodology Connect tool for the Open Verification Methodology (OVM) community. UVM Connect 2.2 can now be compiled to run with the OVM. The UVM Connect architecture facilitates easy connection with other environments beyond the initially supported UVM and SystemC. With the updated UVM Connect, teams using OVM can connect with SystemC models and other environments.

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Mentor Graphics Introduces Questa Functional Verification Platform v10.1

Mentor Graphics rolled out version 10.1 of their Questa functional verification platform. The 10.1 release features increased simulation and verification performance, enhanced support of the Universal Verification Methodology (UVM), accelerated coverage closure, and low power verification with comprehensive Unified Power Format (UPF) support. Questa functional verification platform is a tightly integrated solution for the functional verification of complex System-on-Chip (SoC), ASIC and FPGA designs.

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Mentor Graphics Introduces UVM Express and UVM Connect

Mentor Graphics is expanding support for the Universal Verification Methodology with UVM Express and UVM Connect. UVM Express is one way to progressively adopt UVM methodology. UVM Connect provides standard TLM 1.0 and TLM 2.0 connectivity between models written in SystemC and UVM SystemVerilog. UVM Express and UVM Connect functionality is available now. They can be downloaded from the Mentor Verification Academy. Verification Academy modules on using UVM (UVM Express and UVM Advanced), training material and online documentation are also available.

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Aldec Riviera-PRO 2010.06 RTL and Gate-level Simulator

Aldec introduced Riviera-PRO 2010.06 RTL and gate-level simulator. Riviera-PRO 2010.06 supports the Open Verification Methodology (OVM) co-authored by Cadence (NASDAQ:CDNS) and the early release of the Universal Verification Methodology (UVM) from Accellera. OVM and UVM provide common building blocks and predefined mechanisms for building reusable and expandable test environments that take full advantage of SystemVerilog verification capabilities. Riviera-PRO 2010.06 verification platform is available now.

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