Mentor Graphics introduced a comprehensive IP to System, UPF-based low-power verification flow. Mentor now has platform-level support of Unified Power Format in both the Questa functional verification platform and the Veloce family of hardware emulators that lets users create a single specification for power intent that is reusable and consistent, and facilitates low-power verification across simulation, formal and emulation.
Mentor Graphics rolled out version 10.1 of their Questa functional verification platform. The 10.1 release features increased simulation and verification performance, enhanced support of the Universal Verification Methodology (UVM), accelerated coverage closure, and low power verification with comprehensive Unified Power Format (UPF) support. Questa functional verification platform is a tightly integrated solution for the functional verification of complex System-on-Chip (SoC), ASIC and FPGA designs.
Magma Design Automation, GLOBALFOUNDRIES, and Virage Logic introduced a Unified Power Format (UPF)-compliant RTL-to-GDSII reference flow. The automated, comprehensive solution streamlines the design and manufacture of ICs that use Virage Logic’s intellectual property (IP) and are manufactured in GLOBALFOUNDRIES’ 65LPe 65-nanometer (nm) low-power process technology. The reference flow is available from Magma, GLOBALFOUNDRIES and Virage Logic upon request.