Tag Archives: UC Berkeley

Low-Power Technology Summit Features Jan M. Rabaey

Cadence Design Systems is holding a Low-Power Technology Summit. The event will be keynoted by UC Berkeley Professor Jan M. Rabaey. He is the author of Low Power Design Essentials (Integrated Circuits and Systems). Rabaey will address power issues that impact today’s chip designers. The one-day technical conference will take place on October 18th at Cadence Design Systems in San Jose, California. The event is free.

Continue reading