ASSET InterTech has published an introductory tutorial on IJTAG. The tutorial explains how the new IEEE P1687 Internal JTAG (IJTAG) standard simplifies and automates the way chip designers manage embedded instruments that perform chip validation and characterization. The article describes the on-chip IJTAG architecture and the two languages defined by the standard, Instrument Connectivity Language (ICL) and Procedural Description Language (PDL). ICL defines the connections among embedded on-chip instruments and PDL is an extension of the Tcl (Tool Command Language) for developing validation, test and debug vectors for execution by IJTAG instruments.
The Design and Verification Conference (DVCon) has issued a call for paper and panel abstract submissions, and tutorial proposals. DVCon wants engineers to present their experiences, solutions and ideas. Paper proposals are due August 15, 2011, tutorial proposals are due September 13th, and panel proposals are due September 19th. DVCon will be held February 27-March 1 in San Jose, California. DVCon 2012 is sponsored by Accellera.
Analog Devices will host a webinar on the fundamentals digital to analog converter (DAC). The 60-minute webcast will take place on May 11, 2011, at 12:00 pm ET. The title of the online seminar is: Fundamentals of Designing with Semiconductors for Signal Processing Applications: Digital to Analog Converters. The ADI webinar is the second part of a three-part tutorial series.
Magma Design Automation is offering a free trial version of the Titan Mixed-Signal Platform and analog design accelerators. The Titan Up! program lets designers use the software for 60 days at no charge. The free trial includes a software download and tutorial. Designers can install the Titan Mixed-Signal Platform, Titan ADX and Titan AVP analog design accelerators. The tutorial guides them through creating and optimizing an analog design circuit using a prepared design example and Magma’s FlexCell analog IP technology.