Synopsys introduced a comprehensive design implementation solution for TSMC’s 16-nanometer (nm) FinFET reference flow. The jointly developed reference flow is built on tool certification currently in TSMC’s V0.5 Design Rule Manual (DRM) and SPICE. The collaboration between the two companies has resulted in a comprehensive FinFET implementation flow that can be deployed for production use by mutual customers.
Synopsys is offering 20nm process technology support for the TSMC 20nm Reference flow. The 20nm process offers measurable power, performance and area benefits. TSMC and Synopsys have collaborated closely from the very early stages of 20 nanometer process development to address the challenges of 20nm design. The results of this collaboration will help designers maximize the benefits of the 20nm process to deliver the designs predictably and on time.
ARM and Cadence Design Systems teamed together to create a solution that uses the Cadence Encounter digital platform to optimize ARM POP intellectual property (IP) technology for the Cortex-A9 processor on the TSMC 40LP process, including ultra low threshold voltage (uLVT). The combined solution is available for license from ARM to accelerate the implementation of ARM processors.
TSMC has given Phase I Certification to Synopsys design implementation tools for TSMC’s 20nm process. Synopsys’ Galaxy Implementation Platform features comprehensive support for TSMC’s latest set of 20-nm design rules. The certified tools from TSMC’s Open Innovation Platform and its ecosystem members help engineers create products that meet aggressive power, performance and area targets.
Synopsys rolled out DesignWare Embedded Memory and Logic Library IP for TSMC’s 28 nanometer high-performance and high-performance for mobile process technologies. The DesignWare Embedded Memories and Logic Libraries for TSMC’s 28HP and 28HPM processes are part of the DesignWare Duet Package, which includes SRAMs, ROMs, standard cells, Power Optimization Kits (POKs) and optional overdrive/low voltage PVTs. The Duet Package for TSMC’s 28HP and 28HPM processes is available now.
Cadence Design Systems and TSMC teamed together on a library characterization reference kit. The Cadence Library Characterizer (Altos Liberate) reference kit for TSMC’s standard cell libraries is now available to TSMC customers for download on TSMC-Online. As a result, TSMC customers can now leverage the same technology used in-house at TSMC with the same setup and constraints, helping them address the specific design challenges created through changes to their standard cell libraries.
Mentor Graphics is teaming with TSMC on a SmartFill solution for TSMC’s manufacturing processes starting at 65nm. As a result of the collaboration, Calibre YieldEnhancer product will support SmartFill functionality. The analysis and automatic filling capabilities of the SmartFill solution enables engineers to achieve IC fill constraints with minimal impact on circuit performance in a single pass without manual customization or modification.
Synopsys introduced 28nm design solutions that integrate manufacturing compliance and system-level prototyping with TSMC Reference Flow 12.0. The extended Reference Flow 12.0 reduces time-to-market and speeds time-to-volume using TSMC’s 28-nm process technology. The design enablement solution features virtual prototyping and high-level synthesis linked to TSMC’s advanced processes, expanded manufacturing compliance capabilities and full support of TSMC’s latest 28-nm design rules and models within Synopsys’ Galaxy Implementation Platform.
Cadence Design Systems has been running their System Realization Webinar Series since last month. There are still three webcasts left in the series: Developing Software for ARM-Based Devices (October 13th), System Realization Services from Cadence (October 20th), and TSMC Reference Flow 11: ESL Focus on High-Level Synthesis (November 3rd). The online seminars address the challenges related to system level methodologies including design, verification, TLM, IP, and software integration.