Tag Archives: TraceAnalyzer

Symtavision Introduces Version 3.4 of SymTA/S and TraceAnalyzer

Symtavision SymTA/S and TraceAnalyzer v3.4

Symtavision released version 3.4 of SymTA/S and TraceAnalyzer. SymTA/S v3.4 includes a comprehensive, new timing design and analysis capability for LIN (Local Interconnect Network), which is a low-cost, distributed networking protocol used mainly in automotive and industrial applications. TraceAnalyzer is a tool for visualizing and analyzing timing data from both measurements and simulations. The tool seamlessly integrates with SymTA/S.

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Symtavision Releases Version 3.1 of SymTA/S and TraceAnalyzer

Symtavision released version 3.1 of SymTA/S and TraceAnalyzer integrated system-level tools for planning, optimizing and verifying embedded real-time systems. Improvements in SymTA/S 3.1 and TraceAnalyzer 3.1 include new Scenario Management, a new FIBEX 3.1 import interface and improved Relative Deadline support. In addition, over 50 functional improvements have been implemented at the request Audi, BMW, Bosch, Daimler, Fiat, General Motors, Infineon and Volkswagen.

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Symtavision SymTA/S 3.0 and TraceAnalyzer 3.0 for Integrated Timing Analysis

Symtavision rolled out SymTA/S 3.0 and TraceAnalyzer 3.0. The latest version of system-level tools features round-trip support for model- and trace-based timing analysis in a seamless environment with a consistent user interface. The model-based design and trace-based verification tools improve design productivity and quality when planning, evolving, implementing and verifying embedded real-time systems.

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Symtavision TraceAnalyzer v1.2 for Visualizing, Analyzing System Timing

Symtavision rolled out version 1.2 of their TraceAnalyzer tool for visualizing and analyzing system timing in terms of the constituent ECUs, controllers, processors, buses and networks. TraceAnalyzer v1.2 offers a 10x speed improvement over the previous version. It also reduces memory requirements by a factor of ten. The tools shows controller and bus schedules with events, blocking and pre-emptions and details the timing chains. Engineers can see the flow of signals and data through the system including data loss and multiple reads of the same data.

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