Tag Archives: Tools

White Paper: An Electrical-Thermal MMIC Design Flow

AWR recently published a white paper about the benefits of co-simulation. The title of the white paper is: An Electrical-Thermal MMIC Design Flow. The technical paper uses an actual design example to discuss the effectiveness of co-simulation between AWR’s Microwave Office high-frequency design software and CapeSym’s SYMMIC thermal analysis tool. An X-band RF power amplifier/low-noise amplifier MMIC for a transceiver application was designed in Microwave Office software and thermal coupling and other issues between the two circuits on the single die were quickly remedied with SYMMIC to produce optimum results.

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Rapita Verification Suite Timing, Optimization, Code Coverage Toolset

Rapita Systems introduced the Rapita Verification Suite (RVS) on-target timing verification, optimization and code coverage toolset. RVS combines on-target timing verification and optimization capabilities with structural code coverage measurement resources. RVS is ideal for critical real-time embedded systems, and comes in two two variants for the aerospace and automotive electronics industries. Qualification kits for DO-178B and ISO 26262 will also be available in July.

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New and Improved: Altia Design 9.2, PhotoProto 2.0 and FlowProto 1.5

Altia rolled out Altia Design 9.2 DeepScreen 6.0, PhotoProto 2.0 and FlowProto 1.5 HMI engineering tools for embedded systems. The tools enable engineers to build user interface models. Altia Design 9.2 DeepScreen 6.0 now supports targets like OpenGL ES 2.x, OpenVG and Linux Framebuffer. FlowProto 1.5 pulls logic and structure out of Microsoft Visio and converts it to XML. PhotoProto 2.0 now features enhanced exporting options, integration capabilities with other tools and improved animation capabilities.

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NI TestStand 2010 Development System

National Instruments launched the NI TestStand 2010, which is a test management software for automated validation and production testing. The NI TestStand 2010 Development System is priced at $3,899 (euro 4,099; 546,000 yen). NI TestStand helps test engineers build a software framework for accelerating the development of test sequences and minimizes the total cost of ownership of maintaining test executive software deployed across many test stations. New features include a Sequence Analyzer, a three-way file diff-and-merge utility, support for new PC technologies and enhanced integration with NI LabVIEW graphical system design software.

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MathWorks Polyspace Embedded Software Verification Tools

MathWorks has updated their Polyspace embedded code verification tools. Polyspace code verifiers detect and prove the absence of overflow, divide-by-zero, out-of-bounds array access, and other run-time errors in source code. Polyspace features improved metrics web dashboard, automated scheduling of verification jobs, e-mail notification and increased code metric support. The MathWorks tools help engineers to select and track embedded software quality metrics and thresholds. Polyspace is ideal for automotive, aerospace, defense, industrial automation, and machinery applications.

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Vector Fabrics vfLabs Previews vfAnalyst Features

Vector Fabrics rolled out vfLabs, which provides access to pre-release versions of vfAnalyst features. The cloud-based tool suite for parallelizing sequential C code gives software engineers an early opportunity to try out new functionality as it is developed. vfLabs enables users to selectively augment the capabilities of the vfAnalyst tool. Over time, features initially provided in vfLabs will migrate out of vfLabs to full production status, being replaced by new features for evaluation. vfLabs will also provide pre-release access to features of future Vector Fabrics tools as they become available. vfLabs is free of charge to vfAnalyst subscribers.

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ZMD ZIOL2401 Starter Kit and Lab Kit

ZMD introduced the ZIOL2401 Starter Kit and Lab Kit. The evaluation tools enables engineers to quickly and easily develop IO-Link master applications and device applications. The evaluations and development tools are built around the ZMD’s ZIOL2401 IO-Link high-voltage driver which supports IO-Link master ports, IO-Link device ports, and standard I/O applications. The ZIOL2401 evaluation tools help designers to reduce the time to production by enabling them to develop and test both the master (controller) and the sensor end of the link. The ZIOL2401 Starter Kit is priced at 49.00 € (69.00 USD), and the Lab Kit at 99.00 € (139.00 USD). The evaluation tools are available now.

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Blue Water Embedded Prism GUI Toolkit for Embedded Systems

Blue Water Embedded launched Prism, which is a GUI suite of development tools optimized for embedded systems. Prism offers developers of embedded graphical user interfaces (GUIs) a software solution for creating complex, high-color depth embedded graphic applications. Prism is ideal for automotive, medical, industrial control, office automation and consumer electronics where user interfaces play an essential role in device design. Prism is available now and delivered with full source code and royalty free. Pricing starts at $2,000 for a Prism development-only license.

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Atrenta SpyGlass-Physical for Early Implementation Analysis

Atrenta launched SpyGlass-Physical tool for early implementation analysis. SpyGlass-Physical provides early estimates of area, power, timing and routability for RTL designers without the need for physical design expertise or tools. The tool helps to achieve performance targets in concurrent block/SoC development processes by using interactive implementation analysis features. The result is enhanced guidance for the actual implementation of both IPs and full-chip SoCs. SpyGlass-Physical is currently in limited deployment.

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Azuro Rubix 1.4 and PowerCentric 5.2 Clock Tree Synthesis Tools

Azuro introduced version 5.2 of PowerCentric clock tree synthesis tool and version 1.4 of Rubix clock concurrent optimization tool. Clock concurrent optimization is a new approach to clock tree synthesis which builds useful skew-based clocks concurrently with performing logic gate sizing and placement. The key defining characteristic of clock concurrent optimization is that the timing picture being considered by all its underlying algorithms is a true propagated clocks view of timing based on real propagation of clock signals through the clock network.

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