Tag Archives: TLM

Mentor Graphics Introduces UVM Express and UVM Connect

Mentor Graphics is expanding support for the Universal Verification Methodology with UVM Express and UVM Connect. UVM Express is one way to progressively adopt UVM methodology. UVM Connect provides standard TLM 1.0 and TLM 2.0 connectivity between models written in SystemC and UVM SystemVerilog. UVM Express and UVM Connect functionality is available now. They can be downloaded from the Mentor Verification Academy. Verification Academy modules on using UVM (UVM Express and UVM Advanced), training material and online documentation are also available.

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Forte Design Systems Cynthesizer Ultra

Cynthesizer Ultra, from Forte Design Systems, is a high-level SystemC synthesis software tightly integrated with their CellMath product family. Cynthesizer and Cynthesizer Ultra are shipping now. Cynthesizer comes standard with Forte’s transaction level modeling (TLM) synthesis capability, complete memory generation subsystem, fixed-point support and streaming interface IP. Cynthesizer Ultra adds the CellMath datapath optimizer and floating-point support. U.S. pricing starts at $275,000. Cynthesizer’s Partitioning and Interface Generator features start at $40,000 (U.S.) as an add-on to Cynthesizer.

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