Tag Archives: Timing

Rapita Verification Suite Timing, Optimization, Code Coverage Toolset

Rapita Systems introduced the Rapita Verification Suite (RVS) on-target timing verification, optimization and code coverage toolset. RVS combines on-target timing verification and optimization capabilities with structural code coverage measurement resources. RVS is ideal for critical real-time embedded systems, and comes in two two variants for the aerospace and automotive electronics industries. Qualification kits for DO-178B and ISO 26262 will also be available in July.

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Magma Talus v1.2 SoC Implementation Solution

Magma Design Automation introduced version 1.2 of Talus integrated circuit (IC) implementation solution. Talus v1.2 helps engineers to implement 1 million to 1.5 million cells per day on large designs or blocks of 2 million to 5 million cells – with crosstalk avoidance, advanced on-chip variation (AOCV) and multi-mode multi-corner (MMMC) analysis enabled. Talus is currently in use for complex 28nm designs. Talus 1.2 features faster, more accurate routing, timing and extraction technologies and advanced capabilities. It improves turnaround time by 5x to 6x.

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LAVIS Layout Visualization Platform, Version 10

TOOL Corporation rolled out version 10 of their LAVIS layout visualization tool. LAVIS v10 features a route trace function that makes it possible to display timing information and easily and visually check the clock tree and other elements. The node tracing function, which allows wire width, inter-node spacing, and other rule checks to be made on a traced node, has been improved as well. LAVIS is a high speed layout visualization platform that supports large data and multiple file formats.

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Synopsys PrimeTime 2009.12 Multicore Signoff Tool

Synopsys introduced PrimeTime 2009.12 static timing and signal integrity (SI) analysis tool. The latest version of PrimeTime features threaded multicore processing and speeds timing signoff by 2x. Synopsys’ PrimeTime 2009.12 tool enables design teams to achieve optimal runtime performance across heterogeneous multicore compute environments by utilizing distributed and threaded multicore processing in tandem.

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Variety MX for Embedded Memories Statistical Timing Model Generator

Variety MX, from Altos Design Automation, is a fast and accurate statistical timing model generator for embedded memories. Variety MX generates instance-specific Liberty models for use by Cadence’s Encounter Timing System GXL, Extreme DA’s Goldtimetm, and Synopsys PrimeTime VX. Variety MX is able to characterize memory sizes that cannot be adequately simulated using brute Monte Carlo methods or even with fast sampling techniques. Variety MX is available now.

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