Tag Archives: testbench

Cadence Incisive Debug Analyzer Reduces Debug Time by 40%

Cadence Design Systems launched the Incisive Debug Analyzer. The new tool is a verification debug solution for RTL, testbench and SoC verification. It helps designers reduce debug time and effort. The Incisive Debug Analyzer integrates seamlessly into existing Incisive debug flows, fully leveraging SimVision for waveform and transaction-level debug. The tool will be released at the end of the year.

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New Version of SynaptiCAD TestBencher Pro

SynaptiCAD rolled out a new verion of TestBencher Pro, which is a VHDL and Verilog system-level testbench generation software. The tool simplifies the process of creating and applying random bus transactions to RTL and gate-level models. The latest version of TestBencher Pro simplifies the creation of testbenches that reside in a different compiled library from the design being tested.

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SynaptiCAD BugHunter Pro VHDL and Verilog Testbench, Debugging Tool

SynaptiCAD rolled out the latest version of BugHunter Pro, which is a VHDL and Verilog testbench generation and debugging tool. The updated version of BugHunter Pro supports 64-bit versions of Mentor Graphics ModelSim and Cadence Incisive simulators. A node-locked license for BugHunter sells for $2500 on Windows. Floating licenses sell for $5000 on Windows and $6000 on Unix. A node locked copy of the WaveFormer/BugHunter product bundle sells for $4000 on Windows.

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Maia Functional Verification Tool

Maia EDA introduced the Maia functional verification tool. Maia uses a description of the expected behavior of a device to automatically create a complete self-checking reactive testbench, so freeing engineers from the time-consuming, complex, and error-prone task of manual testbench creation. The tool has been designed to enable both engineers and non-engineers to quickly verify modules and sub-systems, and is initially being offered without cost by the company, allowing trial without registration or risk.

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