Synopsys introduced the Virtualizer Development Kit for Renesas RH850 microcontrollers. The VDK accelerates software development, system integration and test for RH850-based automotive applications such as body, powertrain/hybrid and chassis/safety control. The new development kit seamlessly integrates into existing software development flows. The VDK makes it easy for engineering teams throughout the automotive supply chain to deploy and achieve higher levels of product reliability, reduce overall development cost and shorten design cycles. The VDK for Renesas RH850 MCU is available now.
XJTAG will hold a free boundary scan training workshop at the UK’s Manufacturing Technology Centre (MTC). The workshop will provide an introduction to boundary scan and to show how the debug, test and programming process can be used throughout the product life cycle. The XJTAG workshop will take place Wednesday, June 12, 2013 in Coventry.
Corelis released a new version of their ScanExpress Boundary-Scan Tool Suite. Version 7.8 of the tool features improved cluster testing support, intelligent BSDL file handling, and a new model-based test coverage. The new version also expands JTAG Embedded Test (JET) support to Texas Instruments AM335x Sitara processors. Current Corelis customers that have a valid maintenance contract can now access the new version 7.8 CD through the Corelis support website.
Avery Design Systems recently introduced their SCSI-Xactor verification IP. SCSI-Xactor targets SCSI Express for high performance PCIe-based SSDs. Avery’s verification IP is a complete solution for SCSI Express core and system design. SCSI-Xactor helps design and verification engineers to quickly and extensively test the functionality of SCSI Express controller-based designs.
Cadence Design Systems introduced their TripleCheck IP Validator. The test suite supports all major logic simulators, and it provides a simulator-independent native SystemVerilog and/or e coverage database that supports both leading test bench languages. Cadence TripleCheck IP Validator is available now for PCIe Gen 3. Cadence has support for several additional protocols in development for release later this year.
ASSET InterTech announced new tools to structurally verify, functionally test, analyze performance margins and debug boards based on the Intel microarchitecture codenamed Haswell. ScanWorks board bring-up will be available in the second quarter of this year. Pricing for a base level ScanWorks platform for embedded instruments starts at $12,000.
National Instruments revealed their 2012 Automated Test Outlook, which is based on NI’s latest research on test and measurement technologies and methodologies. National Instruments’ 2012 Automated Test Outlook is based on input from academic and industry research, user forums and surveys, business intelligence and customer advisory board reviews. NI’s report provides information about trends affecting industries like consumer electronics, automotive, semiconductor, aerospace and defense, medical devices and communications.
AdaCore introduced the GNATtest unit test harness generator for Ada. GNATtest is included in GNAT Pro and supports all versions of Ada and all target configurations. It is based on, and replaces, the earlier AUnit technology. The AdaCore GNATtest tool helps automate the essential, but tedious and error-prone, processes for developing and managing the large number of test cases that accompany the verification of large software systems.
Mentor Graphics introduced emulation solutions to accelerate the verification of Universal Serial Bus (USB) SuperSpeed (3.0) products. The hardware and software solutions enable engineers to test USB SuperSpeed peripheral devices integrated on System-on-Chip (SoC) designs, and to develop and test their software drivers and firmware prior to silicon being available. The solution is available now for deployment.
AWR has a new application note that explains how EDA tool integration benefits designers of circuits for 3G and 4G wireless systems. The app note describes the benefits of using AWR’s Microwave Office and Visual System Simulator (VSS) high-frequency design software with National Instruments’ LabVIEW signal processing software and virtual instruments. The title of the paper is Using LabVIEW in the AWR Design Environment To Design Complex Circuits for Wireless Applications.