The ConnX BBE16, from Tensilica, is a second generation baseband engine for LTE (long-term evolution) and 4G baseband SOC (system-on-chip) designs. The ConnX BBE16 is an ultra-high performance 16-MAC fixed-point DSP engine. It is based on an 8-way SIMD (Single Instruction, Multiple Data), 3-issue VLIW (Very Long Instruction Word) architecture with two 128-bit load/store units. It is a click-box configuration option with the configurable Xtensa LX3 processor core. Designers can also choose from a number of other configuration options (memories, interfaces, etc.) when designing their core. The ConnX BBE16 and an evaluation kit will be available in the second quarter of 2010.
Tensilica announced the ConnX Atlas LTE (Long-Term Evolution) reference platform. ConnX Atlas LTE is a heterogeneous seven-core reference architecture for a complete multi-standard programmable radio for advanced mobile devices. Atlas is designed to support the 3GPP (3rd Generation Partnership Project) LTE standard and other complementary standards such as HSPA+ (Evolved High-Speed Packet Access), in a single platform. General availability of the platform will occur in early 2011.
Tensilica launched HiFi EP, which is a superset of the HiFi 2 architecture that is optimized for simultaneous multichannel codec support and/or continuously expanding audio pre- and post-processing in home entertainment products such as Blu-ray Disc players, digital television (DTV), and Smartphones. HiFi EP has also been enhanced for efficient, high-quality voice pre- and post-processing. The enhancements result in up to 40% lower power and up to a 50 percent size reduction.
CoWare and Tensilica teamed together to further enhance the integration of Tensilica’s processor models into the CoWare tools to support CoWare’s advanced functionality to ease software development on multi-core Tensilica-based SOC (system-on-chip) designs. The enhanced solution is being used by joint CoWare-Tensilica customers in automotive, consumer, and wireless markets. Tensilica Xtensa and Diamond Standard PSPs are available immediately from CoWare as part of the CoWare Model Library.
Tensilica introduced pin-level SystemC models of the Xtensa customizable dataplane processors (DPUs). The pin-level models are a natural extension of Tensilica’s pre-existing transaction-level (TLM) Xtensa SystemC models (XTSC). They enable designers to conduct deep simulations of the interaction between the DPUs and special-function RTL (register-transfer-level) hardware blocks at a cycle-by-cycle pin-accurate level within their existing RTL simulators. The models also do not require the usage of any specialized hardware/software co-simulation tool.
Tensilica is offering a webinar on the the five pitfalls of 4G baseband SOC design. The webcast will take place on Tuesday, October 27, 2009 at 11 am PT (2 pm ET). The webinar explores five significant challenges faced by designers of efficient digital basebands, including pitfalls in LTE’s many modes, excessive cost and power, the “million MIPS” hurdle of Turbo decoding, and the dilemma of choosing the right communications among the LTE building blocks. The online seminar uses detailed examples from an end-to-end LTE PHY baseband architecture to highlight the key dos and don’ts.
Tensilica announced the Xtensa 8 customizable processor. The Xtensa 8 low-power dataplane processor core (DPU) starts at a size of only 15,000 gates, consuming less than 0.05mm squared in 40nm process technology. It is one of the smallest licensable controller cores on the market. With power dissipation starting at only 12 µW/MHz, it is also one of the lowest power licensable 32-bit architectures. The Xtensa 8 customizable processor will be available later this month.