Tensilica announced their imaging and video dataplane processor. The IVP DSP architecture supports very high-quality image and video capture using advanced single-frame and multi-frame processing. The IP core supports increasing sensor resolutions. The IVP DPU is available for broad licensing now. The core is ideal for the complex image/video signal processing functions in mobile handsets, tablets, digital televisions (DTV), automotive, video games and computer vision based applications.
Tensilica announced their HiFi Mini DSP IP core. According to the company, the digital signal processor core is the smallest, lowest power DSP IP core supporting always listening voice trigger and speech command modes. The HiFi Mini DSP IP core will be available in March 2013. The core is ideal for smartphones, tablets, appliances, and automotive applications.
Tensilica introduced their ConnX BBE32UE digital signal processor IP core. The ConnX BBE32UE DSP core is ideal for baseband SOC (system-on-chip) designs. Coupled with Tensilica Baseband Dataplane processors (DPUs), the new core can help engineers realize a fully software programmable, flexible modem for LTE-Advanced user equipment category 7 PHY (Layer 1) in less than 200mW (28 nm HPL process). The ConnX BBE32UE is available now for early access customers. General product release is planned for the third quarter of 2012.
Tensilica introduced the HiFi 3 audio/voice digital signal processor intellectual property core for system-on-chip design. HiFi 3 DSP has an 80% increase in performance for the FFT (fast Fourier transform), FIR (finite impulse response), and IIR (infinite impulse response) math functions that are essential in audio pre- and post-processing. In addition, there’s a performance improvement of over 150% for most voice codecs compared to HiFi EP. The HiFi 3 has been delivered to lead customers. General availability will be in March.
The Xtensa LX4 DPU (dataplane processing unit), from Tensilica, features local data memory bandwidth of up to 1024 bits per cycle, wider VLIW (very long instruction word) instructions up to 128 bits for increased parallel processing, and a cache memory prefetch option for reducing cycle counts. The base Xtensa LX4 DPU can reach speeds of over 1 GHz in 45 nm process technology (45GS) with an area of just 0.044 mm2. The configurable and extensible Xtensa LX4 DPU is available now. The IP core is ideal for handling complex compute-intensive DSP applications where an RTL implementation may be the only other option.
The IntegrIT NatureDSP Math library is now available for Tensilica’s HiFi Audio DSPs for system-on-chip (SOC) design. The NatureDSP Math library simplifies the software development process for design teams that want to port software codecs to the Tensilica HiFi Audio DSP. The IntegrIT Nature DSP Signal+ is a collection of signal processing routines needed for implementation of typical digital signal processing functions which efficiently utilize the HiFi Audio DSP architecture. It contains highly optimized routines for filtering, FFT, matrix, trigonometric and other math operations.
Tensilica’s HiFi Audio DSP family of IP (intellectual property) cores for SOC (system-on-chip) design now features the Free Lossless Audio Codec (FLAC) decoder. FLAC is an audio format similar to MP3, but lossless so the audio is compressed without any loss in quality. It is not a proprietary format. As a result, FLAC is not encumbered by patents, and has an open-source reference implementation. Tensilica’s FLAC decoder supports both stereo and multi-channel formats.
Tensilica announced Revision C of the ConnX 545CK 8-MAC (multiply-accumulate) VLIW (very long instruction word) DSP (digital signal processor) core for system-on-chip (SOC) designs. In 65GP optimized for high speed, the ConnX 545CK delivers over 600 MHz operation. The third generation dataplane processor (DPU) core deliver up to 20% faster clock speed, 11% smaller die and up to 30% lower power consumption. The ConnX 545CK Revision C is available now.
COOL Chips International Symposium will take place April 14-16, 2010 in Yokohama, Japan. The COOL Chips symposium covers leading-edge technologies in all areas of microprocessors and their applications. The conference is sponsored by the Technical Committees on Microprocessors and Microcomputers and Computer Architecture of the IEEE Computer Society.
Tensilica launched the third generation of their Diamond Standard controllers. The Diamond Standard processor cores is based on a common Xtensa architecture and provides the price/performance/low-power required for a wide range of embedded control functions in today’s compute-intensive dataplane functions. Improvements in this third generation of Diamond Standard controllers deliver up to 15% faster clock speed, up to 20% smaller die area and up to 15% less power consumption. The Diamond Standard processors are available now.