Synopsys has developed a new test technology to further reduce the cost of testing silicon devices by delivering up to 3x higher test compression and minimizing the time required to test each silicon die. The new test technology is embedded in Synopsys’ Design Compiler RTL synthesis and TetraMAX ATPG solutions. Synopsys’ synthesis-based test innovation will help engineers meet more stringent test cost and quality goals within tighter design schedules.
Cadence Design Systems is holding a Low-Power Technology Summit. The event will be keynoted by UC Berkeley Professor Jan M. Rabaey. He is the author of Low Power Design Essentials (Integrated Circuits and Systems). Rabaey will address power issues that impact today’s chip designers. The one-day technical conference will take place on October 18th at Cadence Design Systems in San Jose, California. The event is free.
The SOI Industry Consortium, CEA-Leti and Soitec are organizing a workshop on fully depleted silicon-on-insulator (FD-SOI) technology for advanced semiconductor architectures. The forum, which includes technical presentations and discussions, will take place in San Francisco, California on February 24, 2012. The event provides semiconductor IC designers and manufacturers with the latest information and insights on using FD-SOI wafers to produce more power efficient ICs at the performance required for applications in mobile and consumer electronics.
Mentor Graphics had issued a call-for-entries for their PCB Technology Leadership Awards competition. The electronic design automation (EDA) competition recognizes engineers and computer aided design (CAD) designers who use Mentor’s technology to address complex printed circuit board systems design challenges, such as small form factor, high-speed content, design team collaboration, advanced PCB fabrication technologies, and design-cycle time reduction. The timeframe for submitting entries is from July 15 – September 24, 2010. Winners will be announced November 9th.
Texas Instruments is hosting an interactive online technology day (eTech Day) on November 17, 2009. The event will feature training sessions from a variety of applications within the embedded and analog processor technologies. TI’s eTech Day is an all-day event that offers networking, presentations, and problem-solving with experts from TI, the TI Developer Network, and the open source community. The event will feature live and on-demand training sessions and office hours where attendees can get real-time answers from TI experts on an array of topics.