Tag Archives: SystemVerilog

Real Intent Ascent Lint v1.2

Real Intent launched Ascent Lint Version 1.2 for early functional verification. Ascent Lint v1.2 performs syntax and semantic Lint checks for complex SoC designs. Ascent Lint now offers rules from STARC Policy, Verilog and SystemVerilog Gotchas, Reuse Methodology Manual (RMM), Principles of Verifiable RTL Designs, and rules based on Real Intent industry expertise.

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Perfectus Technology PCI Express Gen3 Verification IP

SystemVerilog-based and Open Verification Methodology (OVM)-compliant PCI Express Gen3 verification IP (Genie-PCIe3 VIP) is now available from Perfectus Technology. Genie-PCIe3 VIP helps designers accelerate the verification of PCI Express Gen3-based products. Genie-PCIe3 features a complete set of intelligent verification components for verifying PCI Express 1.1/2.0/3.0 and SR-IOV-based designs and it works in any verification environment, including SystemVerilog and OVM methodology. PCIe Gen3 VIP is available immediately.

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