Tag Archives: SystemVerilog

Mentor Graphics Debuts Questa, Veloce ARM AMBA 5 CHI and AMBA 4 ACE Tools

Mentor Graphics has added cache coherent interconnect subsystem verification to the Questa and Veloce platforms. ARM AMBA 5 CHI and AMBA 4 ACE specifications enable high performance, coherent SoC design functionality to be at the heart of the Questa and Veloce platforms. The Questa and Veloce platform AMBA 4 ACE verification solutions are available now. The AMBA 5 CHI verification solutions are available to approved ARM AMBA 5 CHI licensees.

Continue reading

OneSpin Solutions Debuts RTL-to-RTL Equivalence Checking Software

OneSpin Solutions launched 360 EC-RTL equivalence checking software. OneSpin’s 360 EC-RTL compares revisions of register transfer level (RTL) code. 360 EC-RTL is part of the OneSpin 360 EC Product Family. It is a RTL-to-RTL equivalence checker used to exhaustively compare two revisions of synthesizable RTL code. The software features robust register, sequential and power optimization verification. 360 EC-RTL is shipping now.

Continue reading

Real Intent Introduces New Version of Meridian Constraints

Real Intent Meridian Constraints

Real Intent introduced the latest version of their Meridian Constraints product for comprehensive design constraint management. This new software release features enhanced speed, analysis and SystemVerilog language support. The new release of Meridian Constraints is available now. Pricing depends on product configuration.

Continue reading

UVM Connect 2.2 Supports Open Verification Methodology

Mentor Graphics Universal Verification Methodology Connect (UVM Connect)

Mentor Graphics has extended their Universal Verification Methodology Connect tool for the Open Verification Methodology (OVM) community. UVM Connect 2.2 can now be compiled to run with the OVM. The UVM Connect architecture facilitates easy connection with other environments beyond the initially supported UVM and SystemC. With the updated UVM Connect, teams using OVM can connect with SystemC models and other environments.

Continue reading

Cadence TripleCheck IP Validator Simplifies and Automates IP Compliance Testing

Cadence TripleCheck IP Validator for Faster IP Compliance Testing

Cadence Design Systems introduced their TripleCheck IP Validator. The test suite supports all major logic simulators, and it provides a simulator-independent native SystemVerilog and/or e coverage database that supports both leading test bench languages. Cadence TripleCheck IP Validator is available now for PCIe Gen 3. Cadence has support for several additional protocols in development for release later this year.

Continue reading

Mentor Graphics Questa Verification IP Supports MIPI Alliance Specifications

Mentor Graphics’ Questa Verification IP (VIP) now supports several MIPI Alliance specifications. This includes CSI, DSI and the recently announced LLI. Questa VIP is a comprehensive solution for SystemVerilog OVM and UVM test benches. Questa VIP support for MIPI protocols is available now for select customers.

Continue reading

Synopsys Introduces Discovery Verification IP Family with VIPER Architecture

Synopsys introduced their Discovery Verification IP (VIP) family. Synopsys VIP is written entirely in SystemVerilog and is based on the new VIPER Architecture. It offers speeds and simplifies the verification of complex protocols and SoC designs. The Synopsys Discovery VIP family includes Protocol Analyzer, which is a unique prothonotary debug environment. Synopsys VIP is available for a variety of protocols, including USB 3.0, ARM AMBA AXI3, AXI4, ACE, HDMI, MIPI (CSI-2, DSI, HSI, etc.), Ethernet 40G/100G, PCI Express, SATA, and OCP.

Continue reading

Synopsys CustomExplorer Ultra for Mixed Signal Verification

Synopsys introduced their CustomExplorer Ultra mixed-signal verification environment. CustomExplorer Ultra is a comprehensive regression and analysis environment. It increases verification productivity and streamlines the verification process for analog and mixed-signal designs. Synopsys CustomExplorer Ultra is part of their Discovery Verification Platform. The CustomExplorer Ultra mixed-signal verification environment is available now.

Continue reading

Aldec Riviera-PRO 2010.06 RTL and Gate-level Simulator

Aldec introduced Riviera-PRO 2010.06 RTL and gate-level simulator. Riviera-PRO 2010.06 supports the Open Verification Methodology (OVM) co-authored by Cadence (NASDAQ:CDNS) and the early release of the Universal Verification Methodology (UVM) from Accellera. OVM and UVM provide common building blocks and predefined mechanisms for building reusable and expandable test environments that take full advantage of SystemVerilog verification capabilities. Riviera-PRO 2010.06 verification platform is available now.

Continue reading

Jasper Design Automation Formal Verification Proof Kits

Jasper Design Automation rolled out Proof Kits for LPDDR1 and LPDDR2, and DDR3 SDRAM. The new LPDDR and DDR3 Proof Kits both speed verification for these high-demand memories, and ensure conformance with industry standards. The new DDR Proof Kits are currently available as a chapter within Jasper Formal Testplanner, and provided at no additional charge to current licensees of Formal Testplanner.

Continue reading