Cynthesizer Ultra, from Forte Design Systems, is a high-level SystemC synthesis software tightly integrated with their CellMath product family. Cynthesizer and Cynthesizer Ultra are shipping now. Cynthesizer comes standard with Forte’s transaction level modeling (TLM) synthesis capability, complete memory generation subsystem, fixed-point support and streaming interface IP. Cynthesizer Ultra adds the CellMath datapath optimizer and floating-point support. U.S. pricing starts at $275,000. Cynthesizer’s Partitioning and Interface Generator features start at $40,000 (U.S.) as an add-on to Cynthesizer.
CoWare’s SystemC-based software development solution now supports Fast Models from ARM for Cortex-A5 and Cortex-M4 processor IP. The CoWare software development solutions already include support for Fast Models from ARM for the Cortex-A9, Cortex-A8, Cortex-R4 and Cortex-M3 processors. The ARM Cortex IA Model Integration Library to enable usage of Cortex-A5, Cortex-A8, Cortex-A9, Cortex-R4, Cortex M3 and Cortex-M4 Fast Models from ARM in CoWare Virtual Platform and CoWare Platform Architect is available from CoWare now.
The Open SystemC Initiative (OSCI) announced the annual European SystemC User Group (ESCUG) meeting. ESCUG will take place Tuesday, March 9, 6:30 pm – 9:30 pm. The meeting will be co-located with the Design, Automation & Test in Europe (DATE) Conference. The event is free to industry professionals and the media. The Open SystemC Initiative (OSCI) is an independent, non-profit organization dedicated to supporting and advancing SystemC as an industry-standard language for electronic system-level (ESL) design.
The Open Virtual Platforms (OVP) initiative released a reference virtual platform of the ARM Integrator development board using OSCI SystemC TLM-2.0 C++. The virtual platform includes all the models needed for the virtual platform to enable users to run Linux. The virtual platform can be executed either in the OVP simulator (OVPsim), or in a SystemC/TLM-2.0 simulation environment using any of the industry SystemC/TLM-2.0 simulators. The virtual platform and all models are free and available as open source.
CoFluent Design has developed a new methodology that combines the OMG’s (Object Management Group) standards UML (Unified Modeling Language), SysML (System Modeling Language), and MARTE (Modeling and Analysis for Real-Time and Embedded Systems) profile. By offering a link from UML to CoFluent Studio and its automatic SystemC code generation, CoFluent Design makes UML models executable and applicable for multicore system virtualization and performance prediction.
CoFluent Studio can now be used for the creation and automatic generation of SystemC models and test cases for the Mentor Graphics Questa functional verification platform. The automatic SystemC transaction-level modeling (TLM) code generation allows reuse of IC and use case models for validating the register-transfer level (RTL) implementation in Questa.
Tensilica introduced pin-level SystemC models of the Xtensa customizable dataplane processors (DPUs). The pin-level models are a natural extension of Tensilica’s pre-existing transaction-level (TLM) Xtensa SystemC models (XTSC). They enable designers to conduct deep simulations of the interaction between the DPUs and special-function RTL (register-transfer-level) hardware blocks at a cycle-by-cycle pin-accurate level within their existing RTL simulators. The models also do not require the usage of any specialized hardware/software co-simulation tool.
The CoWare SBL-301 SystemC Bus Library for Platform Architect enables early configuration, exploration, and optimization of next-generation system-on-chip (SoC) architectures using AMBA technology-based virtual platforms in SystemC. The new CoWare SBL-301 SystemC Bus Library and architecture design solution featuring CoWare Platform Architect and AMBA designer ADR-301 is available for early customer evaluation now. Production release is expected in December 2009.