Tag Archives: SystemC

Mentor Graphics Debuts Questa, Veloce ARM AMBA 5 CHI and AMBA 4 ACE Tools

Mentor Graphics has added cache coherent interconnect subsystem verification to the Questa and Veloce platforms. ARM AMBA 5 CHI and AMBA 4 ACE specifications enable high performance, coherent SoC design functionality to be at the heart of the Questa and Veloce platforms. The Questa and Veloce platform AMBA 4 ACE verification solutions are available now. The AMBA 5 CHI verification solutions are available to approved ARM AMBA 5 CHI licensees.

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Calypto to Host Webinars on High Level Synthesis and RTL Power Optimization

A Practical Comparison Between C++ and SystemC for High Level Synthesis Webinar

Calypto Design Systems will host two webinars next month. The online seminars will educate designers on the latest in high level synthesis (HLS) and power optimization techniques for RTL-based designs. The titles of the webcasts are Minimizing RTL Power through Sequential Analysis, and A Practical Comparison Between C++ and SystemC for High Level Synthesis.

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Forte Design Systems Launches New Version of Cynthesizer SystemC High-level Synthesis

Cynthesizer SystemC high-level synthesis (HLS) ~ Forte Design Systems

Forte Design Systems launched a new version of Cynthesizer SystemC high-level synthesis (HLS). Cynthesizer v4.3 features improvements in power results and ease of use while expanding their CynWare IP library. This enables design teams to quickly adopt high-level synthesis. New features include new modeling style support, expanded optimization and analysis capabilities, integration with third-party tools and improvements to CynWare intellectual property (IP) cores. Version 4.3 of Forte Cynthesizer is shipping now.

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UVM Connect 2.2 Supports Open Verification Methodology

Mentor Graphics Universal Verification Methodology Connect (UVM Connect)

Mentor Graphics has extended their Universal Verification Methodology Connect tool for the Open Verification Methodology (OVM) community. UVM Connect 2.2 can now be compiled to run with the OVM. The UVM Connect architecture facilitates easy connection with other environments beyond the initially supported UVM and SystemC. With the updated UVM Connect, teams using OVM can connect with SystemC models and other environments.

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OCP-IP Announces Version 2_2x2_2 of the OCP Modeling Kit

Open Core Protocol International Partnership (OCP-IP) released the latest version of the OCP Modeling Kit. Version 2_2x2_2 of the kit features greater robustness of data in payload event queues, a modification of thread-busy signaling API, added support for interrupts, sideband error signaling, sideband user flags, added TLM2-native adapters between TL3 and TL1, and added TLM2-native adapters between TL1 and RTL signals (TL0).

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Updated SynaptiCAD BugHunter Supports C++ and SystemC

The SynaptiCAD BugHunter graphical test bench generator and HDL debugger now supports SystemC and C++. Standalone SystemC and mixed SystemC/Verilog/VHDL simulations can be compiled and debugged under the BugHunter GUI. A node-locked license for BugHunter sells for $2500 on Windows. Floating licenses sell for $5000 on Windows and $6000 on Unix.

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TLM-2.0 Kit for AMBA – Modeling AMBA Protocols in SystemC TLM-2.0

Carbon Design Systems announced a TLM-2.0 solution for the AMBA protocol. The solution enables modeling the AMBA protocols with SystemC TLM2-0. The TLM-2.0 for the AMBA protocol solution will execute in any SystemC environment and contains no runtime licensing. Engineers can create models representing AMBA intellectual property (IP) blocks at any level of abstraction. The TLM-2.0 for the AMBA protocol solution is available for free from Carbon’s IP Exchange.

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Synopsys Platform Architect with Multicore Optimization Technology

Synopsys Platform Architect now features Multicore Optimization Technology. Platform Architect with Multicore Optimization Technology is ideal for performance analysis and early definition of multicore system architectures in SystemC. The new solution enables SoCs, chipsets and systems designers to capture hardware/software performance models of multicore system architectures in the early concept phase for robust performance measurement and trade-off analysis, months prior to software availability.

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OCP-IP Transaction Generator Tool

Open Core Protocol International Partnership (OCP-IP) introduced the Transaction Generator (TG). The tool is a transaction level (TL) SystemC simulator for benchmarking network-on-chips (NoCs) used in multiprocessor system-on-chip (SoC) applications. The Transaction Generator speeds the simulation of large systems. The results obtained at this higher level can be accurately used as an initial estimate in selecting and fine-tuning NoCs. The tool is freely available to both OCP-IP members and non-members alike through GNU LGPL.

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SystemC Japan 2010

The Open SystemC Initiative will hold the first SystemC Japan on Friday, July 2 in Yokohama, Japan. The one-day industry event will feature technical presentations on the use of SystemC for system-level design from industry experts and suppliers, highlighted by user case studies. The agenda features six technical user presentations by top Japanese electronics companies and four informative presentations from leading suppliers of electronic design automation tools and technologies.

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