Tag Archives: system

Synopsys Introduces Virtualizer Development Kits for Renesas Microcontrollers

Synopsys and Renesas teamed together to developed Virtualizer Development Kits. The VDKs for Renesas’ RH850 MCUs are software development tools that integrating functional models of digital hardware. The VDKs help engineers speed software development and system testing for Renesas RH850-based designs. The new VDKs for Renesas’ RH850 MCUs will be available from Synopsys in the fourth quarter of this year.

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WinA&D 7.0 Features Flowcharts and Multiple Dictionary Projects

Excel Software launched version 7.0 of their WinA&D tool for requirements management, system and software design, code generation and flexible report generation. WinA&D 7.0 includes flowcharts, general enhancements to all diagram types and scriptable reports, advanced DFD features and the ability for large projects to use multiple data dictionaries. The Standard edition is $495, Desktop edition $1195 and Developer edition $1995 with Site Licenses available. WinA&D includes printed and PDF user guides.

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Cadence Allegro v16.5 PCB and IC Tool

Cadence Design Systems announced version 16.5 of their Allegro PCB and IC packaging technology. Allegro v16.5 features advanced miniaturization capabilities, integrated power delivery network analysis, DDR3 design-in kit, improved co-design, and flexible team-design enablement. The new features and capabilities improve the path to co-design and analysis between engineers involved in Silicon, SoC, and System Realization. Cadence Allegro 16.5 will be available in late May. Allegro 16.5 technology will also be available through product configuration with on-demand features for specific design tasks.

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White Paper ~ End-To-End System Design: Advantages of an Integrated Tool

AWR Corporation published a new system planning white paper. The AWR white paper outlines the benefits of using a commercial, specialized software program such as Visual System Simulator (VSS) for end-to-end system design, while also embracing legacy approaches with the incorporation of spreadsheet views. The technical paper is available now for AWR.

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SEMATECH, Zeiss Develop PROVE Registration, Overlay Metrology System

Carl Zeiss Semiconductor Metrology Systems (SMS) division’s registration and overlay metrology system has successfully passed a key development milestone. The system, called PROVE, was developed by both SEMATECH and Carl Zeiss. The two companies demonstrated the measurement capability for advanced photomasks for the 32 nm node and below. In a series of test runs, 0.5 nm repeatability and 1.0 nm accuracy in image placement, registration and overlay measurement were verified.

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Docea Power Aceplorer 2.0 and AcePowerModeler

Docea Power introduced Aceplorer 2.0 and AcePowerModeler. Aceplorer is a system-level power and thermal modeling tool. AcePowerModeler is a power model generator tool that closes the loop between implementation and architectural modeling by automating the creation of power models from lower level simulation and characterization data. Aceplorer 2.0 is available now. AcePowerModeler is available now for select customers, and will be released in Q4. It can be used with Aceplorer or stand alone.

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Cadence Palladium XP Verification Computing Platform

Cadence Design Systems launched the Palladium XP verification computing platform. The solution integrates simulation, acceleration and emulation into a single verification environment. Cadence Palladium XP helps engineers design, verify, and integrate hardware and software. The Palladium XP verification computing platform is available now worldwide. It is offered in two configurations, XL for design teams, and GXL for enterprise-class global teams.

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System Optimization Techniques for Peak SoC Performance Webinar

Sonics and JEDA Technologies have an on-demand webinar for optimizating SoC performance. The webcast, System Optimization Techniques for Peak SoC Performance, is ideal for IC, system, and SoC designers working on next-generation silicon for advanced digital entertainment and mobile devices. The presenters are Ravi Chopra (Application Engineer, Sonics) and Andrea Kroll (VP of Marketing and Business Development, JEDA Technologies).

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AWR Hardware in the Loop White Paper

When simulating a complete subsystem (such as a wireless communication device or radar receiver), the quality of measurement data becomes essential to ensure that the finished product meets or exceeds the demands the system will encounter in service. The measurement data can be used to make changes to the system early in the design process, when those changes can be realized in the least amount of time and at the lowest cost. However, this can be accomplished only if there is a direct link between the system being simulated and the measurement equipment itself.

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