Tag Archives: System Verilog

Cadence Mixed-Signal Technology Summit 2013

Cadence Design Systems is holding their Mixed-Signal Summit next week. The event will give attendees the opportunity to learn from experts at Cadence and other leading companies about the latest mixed signal design methodologies, and new Cadence technologies such as support for System Verilog real number modeling based on the IEEE P1800 standard. The free day-long event will take place at its San Jose headquarters on October 10th.

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