Tag Archives: system-on-chip

Carbon Design Systems Launches Performance Analysis Kits

Carbon Performance Analysis Kits (CPAK) ~ Carbon Design Systems

Carbon Design Systems is accelerating the analysis, optimization and verification of system-on-chip (SoC) performance with their new Carbon Performance Analysis Kits (CPAK). The CPAK family for ARM Cortex processors includes reference hardware and software designs along with analysis and debug software for the Cortex-A9, Cortex-A15 and Cortex-A7 cores, and the ARM big.LITTLE subsystem. The CPAK Family for ARM Cortex A-Series Processors will be available in bare metal and Linux configurations in this quarter. Android configurations will be available in the second half of this year.

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Mentor Graphics Introduces Questa Functional Verification Platform v10.1

Mentor Graphics rolled out version 10.1 of their Questa functional verification platform. The 10.1 release features increased simulation and verification performance, enhanced support of the Universal Verification Methodology (UVM), accelerated coverage closure, and low power verification with comprehensive Unified Power Format (UPF) support. Questa functional verification platform is a tightly integrated solution for the functional verification of complex System-on-Chip (SoC), ASIC and FPGA designs.

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Tensilica Unveils ConnX BBE32UE Digital Signal Processor IP Core

Tensilica introduced their ConnX BBE32UE digital signal processor IP core. The ConnX BBE32UE DSP core is ideal for baseband SOC (system-on-chip) designs. Coupled with Tensilica Baseband Dataplane processors (DPUs), the new core can help engineers realize a fully software programmable, flexible modem for LTE-Advanced user equipment category 7 PHY (Layer 1) in less than 200mW (28 nm HPL process). The ConnX BBE32UE is available now for early access customers. General product release is planned for the third quarter of 2012.

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Synopsys Introduces Discovery Verification IP Family with VIPER Architecture

Synopsys introduced their Discovery Verification IP (VIP) family. Synopsys VIP is written entirely in SystemVerilog and is based on the new VIPER Architecture. It offers speeds and simplifies the verification of complex protocols and SoC designs. The Synopsys Discovery VIP family includes Protocol Analyzer, which is a unique prothonotary debug environment. Synopsys VIP is available for a variety of protocols, including USB 3.0, ARM AMBA AXI3, AXI4, ACE, HDMI, MIPI (CSI-2, DSI, HSI, etc.), Ethernet 40G/100G, PCI Express, SATA, and OCP.

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International SoC Conference

The 9th International System-on-Chip (SoC) Conference will take place November 2 and 3, 2011 at the Radisson Hotel Newport Beach, California. The SoC features technical presentations, exhibits, IEEE-OC Tech Job Fair, networking opportunities, panel discussions, keynotes, and IEEE-OC Student Design Contest. The International SoC Conference is ideal for engineers involved in designing new ICs or IPs on a worldwide basis.

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Apache Design Solutions Offers Low-power Webinars

Apache Design Solutions is offering a series of low-power webinars. The webcasts will cover low power methodologies, IP integration, chip-package-system solutions, RTL power analysis, SoC power integrity, analog mixed-signal power noise, full-chip ESD integrity, and IC package power. The eight online seminars will take place at 11am (PDT) in the months of July and August.

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Magma Design Automation Silicon One Initiative

Magma Design Automation announced their Silicon One initiative. Silicon One features differentiated solutions and technologies for improving time to market, product differentiation, cost, power and performance. The goal of the initiative is to make silicon profitable for chip makers. The Silicon One initiative currently focuses on five types of devices: ASIC/ASSP, Analog/Mixed-Signal, Memory, Processing Cores, and System-on-Chip.

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Cadence Wide I/O Memory Controller IP Core

Cadence Design Systems introduced a licensable, wide I/O memory controller core for mobile applications like smartphones and tablets. The new Cadence IP core delivers up to four times the performance of conventional memory interfaces. The wide I/O memory controller and supporting VIP are available now. According to Cadence, the IP is already in use by a high-profile customer on two separate projects.

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Arteris and EVE Design Flow for System-on-Chip Development

Arteris and EVE teamed together on an integrated solution for system-on-chip (SoC) developers. The design flow enables engineers to generate and use actual SoC register transfer level (RTL) implementations on EVE’s ZeBu-Server emulation platform. The integration flow helps SoC developers create and ship products sooner.

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SpringSoft Siloti Visibility Automation System

SpringSoft rolled out the latest version of Siloti Visibility Automation System. The tool features a streamlined, easy-to-use flow for system-on-chip (SoC) verification and debug. It also includes a new reusable behavior analysis database to eliminate redundant analysis cycles and speed up design preparation time by over 10X (compared to previous version). The new version of the Siloti Visibility Automation System is available now. Prices start at $26,400 for a three-year subscription license.

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