Forte Design Systems launched a new version of Cynthesizer SystemC high-level synthesis (HLS). Cynthesizer v4.3 features improvements in power results and ease of use while expanding their CynWare IP library. This enables design teams to quickly adopt high-level synthesis. New features include new modeling style support, expanded optimization and analysis capabilities, integration with third-party tools and improvements to CynWare intellectual property (IP) cores. Version 4.3 of Forte Cynthesizer is shipping now.
AWR published a new application note about the synthesis and design of complex filters. The app note uses a hairpin bandpass filter to illustrate how AWR’s iFilter synthesis software in conjunction with Microwave Office high-frequency design software and AXIEM 3D planar electromagnetic (EM) solver can help designers create filters that conform to specific manufacturing constraints and costs. The title of the paper is Synthesizing and Optimizing a Hairpin Bandpass Filter with AWR Tools.
Synopsys introduced 28nm design solutions that integrate manufacturing compliance and system-level prototyping with TSMC Reference Flow 12.0. The extended Reference Flow 12.0 reduces time-to-market and speeds time-to-volume using TSMC’s 28-nm process technology. The design enablement solution features virtual prototyping and high-level synthesis linked to TSMC’s advanced processes, expanded manufacturing compliance capabilities and full support of TSMC’s latest 28-nm design rules and models within Synopsys’ Galaxy Implementation Platform.
SynaptiCAD recently published a white paper that describes how their updated Gates-on-the-Fly (GOF) was used to find and fix failures identified by Cadence’s Conformal tool. SynaptiCAD’s Verilog netlist editor was updated to support easy correction of logic equivalence failures introduced during modifications to post-synthesis netlists, using equivalence check reports from either Cadence’s Conformal LEC or Synopsys’s Formality. Gates-on-the-Fly graphically analyzes and edits large Verilog netlists that have been generated from a synthesis or layout tool.
Azuro introduced version 5.2 of PowerCentric clock tree synthesis tool and version 1.4 of Rubix clock concurrent optimization tool. Clock concurrent optimization is a new approach to clock tree synthesis which builds useful skew-based clocks concurrently with performing logic gate sizing and placement. The key defining characteristic of clock concurrent optimization is that the timing picture being considered by all its underlying algorithms is a true propagated clocks view of timing based on real propagation of clock signals through the clock network.
Cynthesizer Ultra, from Forte Design Systems, is a high-level SystemC synthesis software tightly integrated with their CellMath product family. Cynthesizer and Cynthesizer Ultra are shipping now. Cynthesizer comes standard with Forte’s transaction level modeling (TLM) synthesis capability, complete memory generation subsystem, fixed-point support and streaming interface IP. Cynthesizer Ultra adds the CellMath datapath optimizer and floating-point support. U.S. pricing starts at $275,000. Cynthesizer’s Partitioning and Interface Generator features start at $40,000 (U.S.) as an add-on to Cynthesizer.
AWR introduced their iFilter technology for synthesis of lumped-element and distributed filters. The module plugs directly into the Microwave Office design environment and is integrated as a wizard within the AWR Design Environment (AWRDE). iFilter is an optional module for Microwave Office software and is available for either lumped-element filter only or for distributed and lumped-element filter synthesis with the 2010 release of AWR Design Environment.
Synopsys introduced Design Compiler 2010. The tool enables RTL designers to perform floorplan exploration within the synthesis environment to efficiently achieve an optimal floorplan. Design Compiler’s new scalable infrastructure tuned for multicore processors results in 2X faster synthesis runtimes on four cores. Design Compiler 2010 reduces iterations and run times in physical implementation.
Synfora is oferring an on-demand webinar that describes the Fundamentals of ESL Synthesis. The webcast will provide RTL designers, systems engineers, and design managers with technical insight into the benefits of high level synthesis, how it operates, and the kinds of transformations that can be made. The online course is presented by Brian Bailey, who is an independent consultant working in the areas of functional verification and ESL. He provides methodology guidance and technical insights to both the EDA industry and the systems industry.
The Open SystemC Initiative (OSCI) released the draft 1.3 standard of the SystemC Synthesis Subset. The Synthesis Subset Draft 1.3 standard is intended for use by logic designers, electronic engineers, and design automation tool developers. It describes a standard syntax and semantics for SystemC synthesis. The Synthesis Subset Draft 1.3 standard is available for download under open-source license.