Synopsys introduced the DesignWare ARC EM Starter Kit for the ARC EM family of embedded processor cores. The DesignWare ARC EM Starter Kit, ARC EM4 and ARC EM6 processor cores and associated development tools are available now. The DesignWare ARC EM4 and ARC EM6 processor cores are optimized for use in embedded and deeply embedded applications such as sensors, storage devices, appliances, consumer electronics, and battery-operated devices where high performance, small size and minimal power consumption are essential.
Synopsys introduced the Virtualizer Development Kit for Renesas RH850 microcontrollers. The VDK accelerates software development, system integration and test for RH850-based automotive applications such as body, powertrain/hybrid and chassis/safety control. The new development kit seamlessly integrates into existing software development flows. The VDK makes it easy for engineering teams throughout the automotive supply chain to deploy and achieve higher levels of product reliability, reduce overall development cost and shorten design cycles. The VDK for Renesas RH850 MCU is available now.
Synopsys recently released a new version of their IC Compiler software. Release 2013.03 features innovations to speed design as well as enables the latest process nodes. IC Compiler 2013.03 includes advanced optimizations to enable high-speed design, efficient implementation of final-stage engineering change orders (ECO) and fully color-ready, tapeout-proven support for the emerging FinFET-based silicon processes.
Synopsys introduced the Virtualizer Development Kit (VDK) for Freescale Semiconductor’s Qorivva microcontroller family. The Synopsys VDK accelerates the development of automotive control applications in powertrain/hybrid, chassis/safety and body electronic control units (ECUs). Synopsys’ automotive VDKs help OEMs and tier-one suppliers to enhance their embedded software development processes by starting earlier, improving productivity and enabling more and better testing in support of safety standards such as ISO 26262. The VDK for Freescale Qorivva MCUs is available now.
Synopsys introduced the Embedded Vision Development System. The new Synopsys is an integrated solution for the acceleration of the design of processors for embedded vision. It is based on Synopsys’ Processor Designer tool set and Synopsys’ HAPS FPGA-based prototyping system. The Embedded Vision Development System is immediately available now.
Synopsys recently introduced their PrimeTime ADV solution. The tool is a new configuration of the PrimeTime static timing analysis and signoff product. PrimeTime ADV increases designer productivity, and enables the lowest leakage power and highest frequency designs to meet today’s aggressive design schedules. PrimeTime ADV features advanced leakage recovery.
Synopsys introduced the latest version of their DesignWare STAR Memory System. The tool is an automated pre- and post-silicon memory test, debug, diagnostic and repair solution. The DesignWare Star Memory System enables designers to improve quality of results (QoR), reduce design time, lower test costs and optimize manufacturing yield. The EDA tool is available now.
Synopsys has added a Performance Checker capability to their next-generation Discovery Verification IP (VIP) for the ARM AMBA 4 AXI4 protocol. The Performance Checker capability in the Synopsys Discovery VIP helps improve the productivity of engineering teams using the AMBA protocols to meet their SoC performance goals.
Synopsys is offering 20nm process technology support for the TSMC 20nm Reference flow. The 20nm process offers measurable power, performance and area benefits. TSMC and Synopsys have collaborated closely from the very early stages of 20 nanometer process development to address the challenges of 20nm design. The results of this collaboration will help designers maximize the benefits of the 20nm process to deliver the designs predictably and on time.
Synopsys recently introduced version 10.5 of the CODE V Optical Design Software, which is an optical engineering and design software. The solution supports the optimization, analysis and tolerancing of image-forming optical systems and free-space photonic devices. CODE V v10.5 includes new and improved optimization and tolerancing features for the design of high-performance optical systems with reduced sensitivity to manufacturing and alignment errors. This helps designers create systems that perform as specified, are less expensive to manufacture and can be assembled faster. CODE V version 10.5 is available now.