Synopsys introduced their new DesignWare ARC EM SEP (Safety Enhancement Package) Processor core for automotive safety-compliant applications. The ARC EM SEP core is configurable to meet the performance, power and area requirements of each target application. Giving designers the ability to define custom instructions facilitates the integration of proprietary hardware accelerators that improve application-specific performance while reducing power consumption and the amount of memory required — critical requirements in embedded automotive designs.
Synopsys introduced a comprehensive design implementation solution for TSMC’s 16-nanometer (nm) FinFET reference flow. The jointly developed reference flow is built on tool certification currently in TSMC’s V0.5 Design Rule Manual (DRM) and SPICE. The collaboration between the two companies has resulted in a comprehensive FinFET implementation flow that can be deployed for production use by mutual customers.
Synopsys released version 10.6 of their CODE V Optical Design Software. CODE V is an optical engineering and design software solution that supports the optimization, analysis and tolerancing of image-forming optical systems and free-space photonic devices. CODE v10.6 enables faster development of new and emerging optical technologies that improves performance CODE V version 10.6 is available now.
Synopsys introduced their DesignWare HDMI 2.0 TX/RX IP solutions. The DesignWare HDMI 2.0 IP solution includes controller, PHY, and example Linux drivers. The solution reduce designers’ integration risk and time-to-market. The DesignWare HDMI 2.0 RX/TX Controller and PHY IP are available now in 28-nm process nodes from multiple foundries.
Synopsys introduced optimized Dolby MS11 Multistream Decoder for the DesignWare ARC AS211SFX and AS221BD audio processors. The MS11 Multistream Decoder is a single-package technology solution for decoding Dolby Digital Plus, Dolby Digital, and Dolby Pulse (AAC LC, HE AAC, and HE AAC v.2) audio formats. The Synopsys Dolby MS11 decoder, optimized for the AS211SFX and AS221BD audio processors, is available now.
Synopsys introduced their DesignWare Sensor IP Subsystem, which is a complete and integrated hardware and software solution for sensor control applications. The DesignWare Sensor IP Subsystem reduces integration effort and cost. The Synopsys DesignWare Sensor IP Subsystem is expected to be available in October of this year to early adopters. General availability is planned for the fourth quarter of 2013.
The Synopsys DesignWare Data Converter IP is available now in the 28-nanometer process node. The data converter IP portfolio includes DesignWare analog-to-digital converters (ADCs), digital-to-analog converters (DACs) and integrated PLLs. The broad DesignWare IP portfolio includes complete interface IP solutions consisting of controllers, PHY and verification IP for widely used protocols, analog IP, embedded memories, logic libraries, processor cores and subsystems.
Synopsys recently launched Formality Ultra, which is a new configuration of the Formality equivalency checking solution. Formality Ultra enables designers to reduce the time and effort required to implement ECOs. This increases schedule predictability and helps engineers close designs on time. The Synopsys tool gives designers the ability to implement more complex functional changes as engineering change orders rather than wait for the next derivative of the design.
Synopsys has extended their DesignWare Duet Embedded Memory and Logic Library IP to enable the optimized implementation of a broad range of processor cores. In one package, designers now have access to the specialty cells and memories they need to optimize their CPU, GPU and DSP cores across the full speed, power and area spectrum. The DesignWare HPC Design Kit will be available for leading 28-nm processes starting in July of this year.
Synopsys has developed a new test technology to further reduce the cost of testing silicon devices by delivering up to 3x higher test compression and minimizing the time required to test each silicon die. The new test technology is embedded in Synopsys’ Design Compiler RTL synthesis and TetraMAX ATPG solutions. Synopsys’ synthesis-based test innovation will help engineers meet more stringent test cost and quality goals within tighter design schedules.