Synopsys introduced a comprehensive design implementation solution for TSMC’s 16-nanometer (nm) FinFET reference flow. The jointly developed reference flow is built on tool certification currently in TSMC’s V0.5 Design Rule Manual (DRM) and SPICE. The collaboration between the two companies has resulted in a comprehensive FinFET implementation flow that can be deployed for production use by mutual customers.
Tanner EDA introduced Tanner Analog FastSPICE (T-AFS), which adds Berkeley Design Automation Analog FastSPICE Platform to Tanner EDA’s full-flow HiPer Silicon design suite. With the availability of Analog FastSPICE as an add-on to Tanner EDA’s analog and mixed-signal design tools, RF designers can realize the benefits of Tanner EDA’s full-flow analog design suite. Analog FastSPICE enables verification of very complex analog/ RF circuits with nanometer SPICE-accurate results.
Texas Instruments released version 9.1 of the TINA-TI SPICE-based analog design and simulation tool. TINA-TI helps engineers design, test and troubleshoot a range of basic and advanced analog circuits, including complex architectures, without any node or number of device limitations. The circuit simulation tool is a fully functional version of TINA, loaded with a library of TI macromodels plus passive and active models. TINA-TI v9.1 is five times faster than verion 7.0. TINA-TI 9.1 is available now.
Synopsys introduced their CustomExplorer Ultra mixed-signal verification environment. CustomExplorer Ultra is a comprehensive regression and analysis environment. It increases verification productivity and streamlines the verification process for analog and mixed-signal designs. Synopsys CustomExplorer Ultra is part of their Discovery Verification Platform. The CustomExplorer Ultra mixed-signal verification environment is available now.
Mentor Graphics launched the Eldo Premier SPICE simulation tool. The Eldo Premier tool accelerates the simulation of large circuits for both pre- and post-layout through the use of proprietary, advanced resolution techniques. Eldo Premier tool features full SPICE accuracy, up to 20X higher performance and 10X better capacity over traditional SPICE. The Eldo Premier tool is available now. The Mentor tool is ideal for applications requiring CPU-intensive transient simulations, such as TFT panels, PLLs and DLLs, frequency synthesizers, delta-sigma converters, ADC/DAC audio and video converters, automotive circuits, DC-DC converters, regulators, power management circuits, and memory-critical path analysis.
Magma Design Automation introduced SiliconSmart ACE Memory Characterization. It features the FineSim Pro simulation technology, dynamic circuit reduction through smart netlist pruning, automatic internal node identification, constraint acceleration, and template-guided function descriptions for vector generation. With SiliconSmart ACE Memory Characterization, integrated circuit (IC) designers can reduce turnaround time and deliver better results for designs targeted at 28-nanometer (nm) and smaller process nodes. SiliconSmart ACE Memory Characterization is an extension to SiliconSmart ACE and is available now.
Magma Design Automation introduced FineSim Fast Monte Carlo, which is a new alternative to traditional Monte Carlo analysis. FineSim Fast Monte Carlo makes it possible to achieve much more accurate statistical analysis as much as 100 times faster than traditional Monte Carlo methods. FineSim Fast Monte Carlo is available now for production use with FineSim SPICE and FineSim Pro for fast, accurate statistical circuit analysis.
AgO introduced AnXplorer, which is a circuit optimization tool for analog and RF design. Its optimization is based on either simulation or equations. The tool works with industry standard SPICE netlists and supports industry standard simulators including Synopsys HSPICE, Cadence Spectre and Legend Design Technology MSIM. It runs on the Linux operating system. Starting with an unsized SPICE netlist, variables for device dimensions and a set of design objectives and constraints, AnXplorer optimizes device sizes by exploring the design space.