Mentor Graphics introduced iSolve SAS and SAS transaction-based verification IP (VIP) solution. iSolve SAS is a plug-and-play hardware interface to the Veloce family of hardware emulators. The VIP solution delivers both a simulation environment, using the Questa verification platform, and accelerated simulation environment using the Veloce hardware for the verification of SAS Gen2-compliant devices. Both solutions are available now for deployment at customer sites.
Cadence Design Systems launched version 16.6 of their Allegro printed circuit board technology. The PCB tool is the first electrical CAD (ECAD) team collaboration environment for PCB design using Microsoft SharePoint technology. Cadence Allegro, integrated with SharePoint, improves team collaboration, design creation and control, and significant productivity improvements. Allegro v16.6 will be available in the fourth quarter of this year.
ARM and Cadence Design Systems teamed together to create a solution that uses the Cadence Encounter digital platform to optimize ARM POP intellectual property (IP) technology for the Cortex-A9 processor on the TSMC 40LP process, including ultra low threshold voltage (uLVT). The combined solution is available for license from ARM to accelerate the implementation of ARM processors.
Synopsys and Renesas teamed together to developed Virtualizer Development Kits. The VDKs for Renesas’ RH850 MCUs are software development tools that integrating functional models of digital hardware. The VDKs help engineers speed software development and system testing for Renesas RH850-based designs. The new VDKs for Renesas’ RH850 MCUs will be available from Synopsys in the fourth quarter of this year.
Apache Design announced four online seminars for this month. The webcasts will cover simulation software platforms and methodologies that meet integrated circuit (IC) power, performance and price demands for low-power mobile, high-performance computing, consumer and automotive electronics. The Apache Low Power Webinar Series will take place July 24, July 25, July 26, and July 31.
Mentor Graphics and MoreThanIP teamed together on emulation solutions for the verification of Multi-Gigabit Ethernet Systems-on-Chips (SoCs). Their solution combines Mentor Veloce hardware emulation technology and the iSolve application solutions with MoreThanIP’s Ethernet 40G/100G MAC/PCS IP Cores. Mentor Graphics is a leader in advanced system verification solutions. MoreThanIP is a leader in delivery of IP products for high-speed communications, serial backplanes, and embedded system technologies.
SpringSoft and Vennsa Technologies teamed together to integrate the SpringSoft Verdi Automated Debug System and Vennsa OnPoint Root Cause Analysis. The seamless interoperability between the two tools enables engineers to increase verification productivity and decrease the chip debug burden. The integrated Verdi and OnPoint platform is available now.
Apache Design Solutions is offering a series of low-power webinars. The webcasts will cover low power methodologies, IP integration, chip-package-system solutions, RTL power analysis, SoC power integrity, analog mixed-signal power noise, full-chip ESD integrity, and IC package power. The eight online seminars will take place at 11am (PDT) in the months of July and August.
At the Microelectronics Packaging and Test Engineering Council (MEPTEC) Technical Symposium, Apache Design Solutions will take part in a technical session, Co-Design Solutions – Bridging the Gap from Silicon to System. The session will focus on fast 3D EM simulations. MEPTEC takes place in San Jose, California, on Thursday, February 25.