Tag Archives: SoC

New Cadence Book: Advanced Verification Topics

Cadence Design Systems published a new book: Advanced Verification Topics. The 229-page book describes the latest techniques and methodologies for verifying today’s most complex IP and systems on chips (SoCs). It discusses topics like metric-driven verification of digital and mixed-signal designs, low-power verification using the UVM, multi-language UVM, and acceleration for the UVM. The Cadence book is ideal for aid verification engineers. It builds on a prior Cadence book, A Practical Guide to Adopting the Universal Verification Methodology (UVM).

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International SoC Conference

The 9th International System-on-Chip (SoC) Conference will take place November 2 and 3, 2011 at the Radisson Hotel Newport Beach, California. The SoC features technical presentations, exhibits, IEEE-OC Tech Job Fair, networking opportunities, panel discussions, keynotes, and IEEE-OC Student Design Contest. The International SoC Conference is ideal for engineers involved in designing new ICs or IPs on a worldwide basis.

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Seminar: Design and Verification in the SoC Era

Mentor Graphics will conduct a technical seminar about the challenges of design and functional verification for complex multi-core SoC designs. The event, Design and Verification in the SoC Era, features keynote sessions delivered by John Goodenough (ARM) and Harry Foster (Mentor Graphics). It will take place on October 18, 2011 in San Jose, California. The Mentor Graphics seminar will run from 9am to 3pm Pacific time.

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Apache Design Solutions Offers Low-power Webinars

Apache Design Solutions is offering a series of low-power webinars. The webcasts will cover low power methodologies, IP integration, chip-package-system solutions, RTL power analysis, SoC power integrity, analog mixed-signal power noise, full-chip ESD integrity, and IC package power. The eight online seminars will take place at 11am (PDT) in the months of July and August.

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Magma Design Automation Silicon One Initiative

Magma Design Automation announced their Silicon One initiative. Silicon One features differentiated solutions and technologies for improving time to market, product differentiation, cost, power and performance. The goal of the initiative is to make silicon profitable for chip makers. The Silicon One initiative currently focuses on five types of devices: ASIC/ASSP, Analog/Mixed-Signal, Memory, Processing Cores, and System-on-Chip.

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Cadence Allegro v16.5 PCB and IC Tool

Cadence Design Systems announced version 16.5 of their Allegro PCB and IC packaging technology. Allegro v16.5 features advanced miniaturization capabilities, integrated power delivery network analysis, DDR3 design-in kit, improved co-design, and flexible team-design enablement. The new features and capabilities improve the path to co-design and analysis between engineers involved in Silicon, SoC, and System Realization. Cadence Allegro 16.5 will be available in late May. Allegro 16.5 technology will also be available through product configuration with on-demand features for specific design tasks.

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Cadence Wide I/O Memory Controller IP Core

Cadence Design Systems introduced a licensable, wide I/O memory controller core for mobile applications like smartphones and tablets. The new Cadence IP core delivers up to four times the performance of conventional memory interfaces. The wide I/O memory controller and supporting VIP are available now. According to Cadence, the IP is already in use by a high-profile customer on two separate projects.

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Mentor 3D TV Multimedia Verification Platform

Mentor Graphics launched their 3D TV Multimedia Verification Platform. The multimedia platform enables designers to develop and test the software against multiple 3D TV formats on their systems-on-chip (SoC) before silicon is available. The 3D TV verification platform supports the latest HDMI and other digital TV standards. The solution consists of the Veloce family of emulators and the iSolve Multimedia product for HTDV and HDMI 3D applications. The Mentor 3D TV multimedia platform is available now.

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Arteris and EVE Design Flow for System-on-Chip Development

Arteris and EVE teamed together on an integrated solution for system-on-chip (SoC) developers. The design flow enables engineers to generate and use actual SoC register transfer level (RTL) implementations on EVE’s ZeBu-Server emulation platform. The integration flow helps SoC developers create and ship products sooner.

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SpringSoft Siloti Visibility Automation System

SpringSoft rolled out the latest version of Siloti Visibility Automation System. The tool features a streamlined, easy-to-use flow for system-on-chip (SoC) verification and debug. It also includes a new reusable behavior analysis database to eliminate redundant analysis cycles and speed up design preparation time by over 10X (compared to previous version). The new version of the Siloti Visibility Automation System is available now. Prices start at $26,400 for a three-year subscription license.

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