Tag Archives: SoC

Synopsys Discovery VIP Features Performance Checker for AMBA 4 AXI4

Synopsys Discovery VIP with Performance Checker capability

Synopsys has added a Performance Checker capability to their next-generation Discovery Verification IP (VIP) for the ARM AMBA 4 AXI4 protocol. The Performance Checker capability in the Synopsys Discovery VIP helps improve the productivity of engineering teams using the AMBA protocols to meet their SoC performance goals.

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Breker TrekSoC Supports Multiple Heterogeneous Embedded Processors

Breker Verification Systems TrekSoC for SoC designs

Breker Verification Systems launched a new verion of TrekSoC for SoC designs. The Breker software now supports multiple heterogeneous embedded processors. The new verification support for multiple heterogeneous processors helps project teams verify their SoCs more completely. The latest release of TrekSoC is available to qualified verification teams now. General availability is expected at the end of 2012.

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Cadence Incisive Debug Analyzer Reduces Debug Time by 40%

Cadence Design Systems launched the Incisive Debug Analyzer. The new tool is a verification debug solution for RTL, testbench and SoC verification. It helps designers reduce debug time and effort. The Incisive Debug Analyzer integrates seamlessly into existing Incisive debug flows, fully leveraging SimVision for waveform and transaction-level debug. The tool will be released at the end of the year.

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EVE Debuts e-zTest MIPI CSI-2 and MIPI DSI Validation Platforms

EVE introduced the e-zTest MIPI CSI-2 and e-zTest MIPI DSI validation platforms. The new application-specific debug solutions support the Mobile Industry Processor Interface (MIPI) Alliance wireless standards for Camera Serial Interface (CSI-2) and Display Serial Interface (DSI). The two new wireless system-on-chip (SoC) validation platforms are the first commercial synthesizable virtual components for SoC emulation that meet MIPI standards. The EVE platforms are available now.

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Synopsys Announces New Hybrid Prototyping Solution

Synopsys integrated hybrid prototyping solution

Synopsys introduced an integrated hybrid prototyping solution. The out-of-box solution features Synopsys’ Virtualizer virtual prototyping and Synopsys’ HAPS FPGA-based prototyping. By integrating the strengths of Virtualizer virtual prototyping with HAPS FPGA-based prototyping using the UMRBus physical link, Synopsys enables designers to develop fully operational SoC prototypes much faster and earlier in the design cycle, and accelerate software development and full system validation. The Synopsys hybrid prototyping solution is available now to early adopters.

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Carbon Design Systems Launches Performance Analysis Kits

Carbon Performance Analysis Kits (CPAK) ~ Carbon Design Systems

Carbon Design Systems is accelerating the analysis, optimization and verification of system-on-chip (SoC) performance with their new Carbon Performance Analysis Kits (CPAK). The CPAK family for ARM Cortex processors includes reference hardware and software designs along with analysis and debug software for the Cortex-A9, Cortex-A15 and Cortex-A7 cores, and the ARM big.LITTLE subsystem. The CPAK Family for ARM Cortex A-Series Processors will be available in bare metal and Linux configurations in this quarter. Android configurations will be available in the second half of this year.

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Mentor Graphics Introduces Questa Functional Verification Platform v10.1

Mentor Graphics rolled out version 10.1 of their Questa functional verification platform. The 10.1 release features increased simulation and verification performance, enhanced support of the Universal Verification Methodology (UVM), accelerated coverage closure, and low power verification with comprehensive Unified Power Format (UPF) support. Questa functional verification platform is a tightly integrated solution for the functional verification of complex System-on-Chip (SoC), ASIC and FPGA designs.

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Tensilica Unveils ConnX BBE32UE Digital Signal Processor IP Core

Tensilica introduced their ConnX BBE32UE digital signal processor IP core. The ConnX BBE32UE DSP core is ideal for baseband SOC (system-on-chip) designs. Coupled with Tensilica Baseband Dataplane processors (DPUs), the new core can help engineers realize a fully software programmable, flexible modem for LTE-Advanced user equipment category 7 PHY (Layer 1) in less than 200mW (28 nm HPL process). The ConnX BBE32UE is available now for early access customers. General product release is planned for the third quarter of 2012.

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Synopsys Introduces Discovery Verification IP Family with VIPER Architecture

Synopsys introduced their Discovery Verification IP (VIP) family. Synopsys VIP is written entirely in SystemVerilog and is based on the new VIPER Architecture. It offers speeds and simplifies the verification of complex protocols and SoC designs. The Synopsys Discovery VIP family includes Protocol Analyzer, which is a unique prothonotary debug environment. Synopsys VIP is available for a variety of protocols, including USB 3.0, ARM AMBA AXI3, AXI4, ACE, HDMI, MIPI (CSI-2, DSI, HSI, etc.), Ethernet 40G/100G, PCI Express, SATA, and OCP.

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Cadence, Samsung Foundry Develop DFM Flows for 32nm, 28nm, 20nm Chip Design

Cadence Design Systems and Samsung Foundry teamed together to create a design-for-manufacturing infrastructure to produce complex chips. Cadence worked closely with Samsung Foundry to integrate their robust DFM suite. The resulting flows and underlying infrastructure provide a significant competitive edge by enabling engineers to meet tight deadlines while reducing the risk of costly errors.

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