Tag Archives: simulator

SLASH Combines SLED Schematic Editor and SMASH mixed Signal Simulator

SLASH, from Dolphin Integration, bundles the SLED schematic link editor with the SMASH mixed signal simulator. SLASH natively supports Property Specification Language (PSL) assertions to empower designers for performing Assertion-Based Verification (ABV). PSL is a language based on the Sugar language which originated at IBM Haifa. It has been IEEE standardized as PSL in 1995. It aims at specifying design properties through assertions to ensure that a circuit meets its specifications.

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Free SynaptiCAD VeriLogger Extreme Verilog 2001 Simulator

SynaptiCAD is giving away free “no strings attached” 6 month licenses for VeriLogger Extreme. For a limited time, free licenses will be available for both Linux and Windows versions of the simulator. Unlike the lower cost simulators typically provided with FPGA tools, SynaptiCAD’s simulator is being distributed without any code that slows down the simulator when run on larger designs, making it run over 10x faster than the competition on larger simulation runs.

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