Cadence Design Systems announced version 16.5 of their Allegro PCB and IC packaging technology. Allegro v16.5 features advanced miniaturization capabilities, integrated power delivery network analysis, DDR3 design-in kit, improved co-design, and flexible team-design enablement. The new features and capabilities improve the path to co-design and analysis between engineers involved in Silicon, SoC, and System Realization. Cadence Allegro 16.5 will be available in late May. Allegro 16.5 technology will also be available through product configuration with on-demand features for specific design tasks.
Cadence Design Systems introduced over 600 new capabilities to improve verification productivity for ASIC and FPGA designers. The capabilities, along with support for the Accellera Universal Verification Methodology (UVM), will expand the scope of metric-driven verification (MDV) to help engineers achieve faster, more comprehensive verification closure and Silicon Realization.
Imec announced large-area (70cm2) epitaxial solar cells with efficiencies of up to 16.3% on high-quality substrates. Efficiencies of up to 14.7% were also achieved on large-area low-quality substrates. The results were achieved within imec’s silicon solar cell industrial affiliation program (IIAP) that explores and develops advanced process technologies aiming a sharp reduction in silicon use, whilst increasing cell efficiency and hence further lowering substantially the cost per Watt peak.
HP Labs researchers have discovered that the memristor is capable of performing logic functions. As a result, it may be possible in the future to have computations performed in chips where data is stored instead of on a specialized central processing unit. A memristor is a resistor with memory that represents the fourth basic circuit element in electrical engineering.
LeCroy introduced SimPASS PE simulation design verification tool for PCI Express 3.0 protocol testing. LeCroy’s SimPASS PE provides designers with a new way to observe and analyze PCI Express-based I/O traffic. SimPASS is ideal for the pre-silicon simulation and design verification phases of development. SimPASS is based on the existing LeCroy graphical user interface for display and analysis of data traffic, and extends the data traffic analysis capabilities commonly used for post silicon testing to the simulation environment. SimPASS for PCI Express is now available.
DOLPHIN Integration announced the Application Hardware Modeling (AHM) for the development of Virtual Components of Silicon IP. AHM aims at optimizing any critical function performed jointly by parts of the system, comprising some Virtual Component within a SoC, its PCB with relevant discrete components, such as Quartz, PMIC, or MEMS, along with application software.