Tag Archives: Silicon Realization

Cadence Mixed-Signal Design Seminars

Cadence Design Systems is offering a series of mixed-signal design seminars. Registration is open in North America now. EMEA and Asia sessions will be open within a few weeks. The events will discuss best practices for realizing highly integrated and complex mixed-signal designs more productively and profitably. The seminars will present case studies about how companies are using Cadence mixed-signal solutions to achieve the tape-out goals, optimize performance and power, reduce costs, improve turnaround time and mitigate chip functionality and quality risks.

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Cadence Digital End-to-end Flow for 28nm Giga-gate/Gigahertz Designs

Cadence Design Systems announced a 28nm digital end-to-end design flow based on Encounter. The digital 28-nanometer flow provides a faster, more deterministic path to achieve giga-gate/gigahertz silicon through technology integration and significant core architecture and algorithm improvements in a unified design, implementation and verification flow. The new Encounter-based flow enables designers to consider the entire chip flow holistically. It supports Cadence’s approach to Silicon Realization, which is a key element of the EDA360 vision. The new flow is available now.

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RTL-to-GDSII Silicon Realization Reference Flow for Common Platform

Cadence Design Systems announced a qualified 32/28-nanometer reference flow for the Common Platform technology. The new Silicon Realization reference flow for the Common Platform alliance is built around the Cadence end-to-end Encounter flow, including Encounter RTL Compiler, Encounter Test, Encounter Conformal, the Encounter Digital Implementation System, Litho Physical Analyzer, QRC Extractor, Encounter Timing System, and Encounter Power System.

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White Paper: Cadence Design Systems Silicon Realization

Cadence Design Systems recently published a white paper on their new Silicon Realization approach. The technical paper explains how Silicon Realization is a fundamentally new approach to semiconductor design, verification, and implementation. Silicon Realization extends traditional EDA to cover both integration and creation. It unites functional, physical, and electrical concerns. It is also based on three emerging concepts: unified intent, higher abstraction levels, and convergence.

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Cadence Silicon Realization Webinars

Cadence Design Systems is offering a series of silicon realization webinars. The webcasts will present new approaches to improving productivity, predictability, and profitability. Attendess will learn how to maximize investment in the UVM, find out how to achieve a predictable and convergent path to closure, learn how to eliminate bugs with formal verification, and enhance design team collaboration. All the online seminars will take place from 10am-11am PST.

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