Cadence Design Systems announced the Tempus Timing Signoff Solution. The Tempus static timing analysis and closure tool enables System-on-Chip (SoC) developers to speed timing closure and move chip designs to fabrication quickly. The Cadence Tempus Timing Signoff Solution is expected to be available in the third quarter of 2013.
Synopsys recently introduced their PrimeTime ADV solution. The tool is a new configuration of the PrimeTime static timing analysis and signoff product. PrimeTime ADV increases designer productivity, and enables the lowest leakage power and highest frequency designs to meet today’s aggressive design schedules. PrimeTime ADV features advanced leakage recovery.
Cadence Design Systems introduced Virtuoso Advanced Node, which is a set of custom/analog capabilities designed for the advanced technology nodes of 20 nanometers and below. Virtuoso Advanced Node enables design teams to optimize designs for performance, power and area while reducing or even eliminating tasks that would make 20nm design much more time consuming and labor intensive.
Mentor Graphics introduced the Calibre RealTime platform. The tool offers signoff verification on demand inside the custom/AMS design creation process. Custom and analog designers can now verify and optimize designs against Calibre signoff decks while editing layouts. With Calibre RealTime, designers can improve both design speed and the quality of results. Calibre RealTime can eliminate the divergence between design tool checking and signoff and make custom designers more productive.
The events will present the latest approaches to realizing silicon — productively and profitably. Engineers will learn about in-design signoff analysis with emphasis on timing, power, extraction, and in-design and DFM signoff at advanced nodes. Designers will also learn about the advanced technology in the latest release of Encounter Digital Implementation (EDI) System with emphasis on maximizing power savings and accelerating design closure.
Cadence Design Systems is offering a series of EDA360 webinars. The digital implementation and signoff webcasts will present the latest approaches to realizing silicon, productively and profitably. The first online event, Getting Back Timing Margins: Traditional OCV Alternatives, starts today at 10am Pacific time. EDA360 supports both design creators and integrators.
Mentor Graphics introduced the Calibre InRoute design and verification platform. Calibre InRoute enables engineers to natively invoke Calibre tools within the Olympus-SoC place and route system to achieve true manufacturing closure during physical design. The Calibre InRoute automatically detects and fixes DRC violations and performs design for manufacturing (DFM) enhancements while optimizing for area, timing, power and signal integrity.
Cadence Encounter Digital Implementation (EDI) System 9.1 is a digital design, implementation, and verification environment for the development of large-scale, complex SoCs. EDI System 9.1 helps designers develop low power and mixed signal SoCs at 32- and 28-nanometer with hundreds of millions of gates, including hundreds of IP elements and embedded processors.
Synopsys introduced PrimeTime 2009.12 static timing and signal integrity (SI) analysis tool. The latest version of PrimeTime features threaded multicore processing and speeds timing signoff by 2x. Synopsys’ PrimeTime 2009.12 tool enables design teams to achieve optimal runtime performance across heterogeneous multicore compute environments by utilizing distributed and threaded multicore processing in tandem.