HSPICE 2011.09 has been integrated with Sigrity’s signal integrity analysis solution to accelerate signal integrity simulation of high-speed systems. The combined Synopsys and Sigrity tool features up to 3X faster simulation of signal and power integrity analysis of multi-gigahertz designs. In addition, HSPICE 2011.09 circuit simulator offers enhanced multi-core simulation performance, improved accuracy in statistical eye-diagram analysis, and new multi-core enabled S-parameter and W-element analysis.
Sigrity launched their SystemSI family of signal integrity analysis solutions. SystemSI is a platform for end-to-end simulations of high-speed signal interfaces. SystemSI – Parallel Bus Analysis is available on Windows and Linux platforms with annual prices starting at $26,500. A Via Wizard for pre-layout studies, using 3D FEM techniques, starts at $8,000 per year. SystemSI – Serial Link Analysis is priced at $26,500 annually.
Altos Design Automation and Extreme DA developed a signal-integrity (SI) design flow for integrated circuit (IC) designs manufactured at process nodes of 65-nanometers (nm) and below. Extreme DA GoldTime for use with Altos Variety and Liberate models is available now from Extreme DA. Pricing varies depending on configuration. Altos Variety and Liberate approved libraries for Extreme DA GoldTime are available now from Altos.
NXP Semiconductors has an archived webinar about maintaining signal integrity when placing ESD devices on high speed differential signals. Topics covered in the webcast include: Capacitance, inductance, and methods of impedance matching, maintaining eye openings, and minimizing jitter and skew. During the online seminar, NXP will compare signal integrity challenges with different ESD solutions.
Synopsys introduced PrimeTime 2009.12 static timing and signal integrity (SI) analysis tool. The latest version of PrimeTime features threaded multicore processing and speeds timing signoff by 2x. Synopsys’ PrimeTime 2009.12 tool enables design teams to achieve optimal runtime performance across heterogeneous multicore compute environments by utilizing distributed and threaded multicore processing in tandem.
Agilent’s Advanced Design System (ADS) 2009 Update 1 features a new statistical mode for the signal integrity Channel Simulator. The new statistical mode is ideal for design and verification of high-speed, chip-to-chip data links found in most consumer and enterprise digital products produced today. By accelerating simulation, the new Channel Simulator mode allows manufacturers of such products to more quickly explore and arrive at an optimal design and eliminates the need for costly and time-consuming prototype iterations, dramatically improving time-to-market.