Tag Archives: Semiconductor

DesignCon 2013 Features Over 100 Tutorials and Technical Paper Sessions

DesignCon 2013 Conference ~ UBM Electronics

DesignCon 2013 will feature over 100 in-depth tutorials, technical paper sessions, panel discussions, presentations and an educational forum. The two-day event is ideal for engineers in the chip, board and systems design community. DesignCon 2013, which is hosted by UBM Electronics, will take place January 28-31 in Santa Clara, California. Early bird pricing for the conference, which provides registrants with $250 in savings, ends on Friday, December 7, 2012.

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Fully Depleted Workshop Covers Fully Depleted SOI Technology

The SOI Industry Consortium, CEA-Leti and Soitec are organizing a workshop on fully depleted silicon-on-insulator (FD-SOI) technology for advanced semiconductor architectures. The forum, which includes technical presentations and discussions, will take place in San Francisco, California on February 24, 2012. The event provides semiconductor IC designers and manufacturers with the latest information and insights on using FD-SOI wafers to produce more power efficient ICs at the performance required for applications in mobile and consumer electronics.

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IPextreme Xena Platform for Semiconductor IP Operations

IPextreme launched Xena, which is a complete, secure, scalable platform for managing semiconductor IP. There are two product offerings: Xena Cloud and Xena Enterprise. With the enterprise version, companies host Xena on their own internal servers, handle administration of the server, and have unlimited numbers of users. With the cloud version, Xena is hosted in the cloud with IPextreme handling the administration of the host server. The company buys subscriptions for its Xena users. In both models, customers of IP providers can use Xena for free.

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White Paper: Cadence Design Systems Silicon Realization

Cadence Design Systems recently published a white paper on their new Silicon Realization approach. The technical paper explains how Silicon Realization is a fundamentally new approach to semiconductor design, verification, and implementation. Silicon Realization extends traditional EDA to cover both integration and creation. It unites functional, physical, and electrical concerns. It is also based on three emerging concepts: unified intent, higher abstraction levels, and convergence.

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MAZeT Simulation Tool for Spectral Selective Semiconductor Sensors

MAZeT announced a new tool for the simulation of compact spectral-selective semiconductor sensors for precise inline measurements. The simulation software helps engineers select the right sensor and optimal combination of filters and illumination. The simulation tool is ideal for validating the requirements of new and existing applications. Some optimizations that are highlighted can be easily implemented, for example, swapping the sensor lighting used or choosing objects for calibration.

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2009 Worldwide Semiconductor Revenues Decreased 9% to $225 Billion

According to International Data Corporation (IDC), 2009 worldwide semiconductor revenues declined to $225.1 billion (decrease of 9%). The top five chip suppliers were Intel, Samsung, Texas Instruments, Toshiba, and Qualcomm. The five suppliers maintained about 34.3% of the semiconductor market. So far, 2010 appears to be very strong. Semiconductor inventory checks indicate strong demand in the first half of 2010 with order rates expected to normalize in the second half of the year. Assuming there are no macroeconomic shocks to global economy, IDC expects 16-18% year-over-year semiconductor revenue growth for 2010.

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SEMATECH Surface Preparation and Cleaning Conference

SEMATECH’s Surface Preparation and Cleaning Conference (SPCC) will feature advanced technologies for cleaning, measuring and processing new III-V semiconductor materials for volume wafer manufacturing. SPCC 2010 will focus on particle removal, including next-generation materials, controlling processes to minimize impact on fragile device structures, non-damaging methods to remove resist, and new metrology approaches for measuring passivation and surface defects. SPCC will take place March 22-24, 2010 at the Sheraton Austin Hotel.

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3D Architectures for Semiconductor Integration and Packaging Conference

The 3-D Architectures for Semiconductor Integration and Packaging Conference will take place December 9-11, 2009, at the Hyatt Regency San Francisco Airport in Burlingame, CA. This year’s conference will provide attendees and speakers the unique opportunity to explore and understand the technology and business implications of the trend toward 3-D device and system integration in the semiconductor industry. At the conference, Si2 will present the findings from a recent 3D Standards workshop hosted by Si2 and GSA.

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