The 2011 International Symposium on Quality Electronic Design (ISQED) features seven keynote speeches, poster sessions, nine tutorials, over 100 technical presentations, and exhibits. The conference will take place March 14-16 at the Hyatt Regency Hotel in Santa Clara, CA. The event is co-located with Sematech’s Design for Reliability Workshop (Stress Management for 3D ICs Using Through Silicon Vias) and the International Electronic Design Education Conference (IEDEC). the ISQED keynote speeches and exhibits are free and open to all.
The 2011 SEMATECH Knowledge Series (SKS) will discuss the challenges and technology developments in next-generation lithography, materials and methods to enhance transistor and back-end development, and ways to improve manufacturing efficiency and yield. The worldwide conferences, symposia, and workshops are designed to enhance global knowledge and collaboration in key areas of nanoelectronics R&D by providing technology forums to explore critical issues and build industry consensus.
International SEMATECH Manufacturing Initiative (ISMI) announced the Total Equivalent Energy Calculator II (TEECalc II). The web-based software tracks and evaluates the energy performance of semiconductor manufacturing equipment in order to reduce energy consumption and improve energy efficiency. TEECalc II helps IC and equipment manufacturers identify areas to make critical energy performance improvements to their process equipment and facilities. TEECalc II capabilities have been expanded and improved from TEECalc I. The TEECalc II is available now.
Carl Zeiss Semiconductor Metrology Systems (SMS) division’s registration and overlay metrology system has successfully passed a key development milestone. The system, called PROVE, was developed by both SEMATECH and Carl Zeiss. The two companies demonstrated the measurement capability for advanced photomasks for the 32 nm node and below. In a series of test runs, 0.5 nm repeatability and 1.0 nm accuracy in image placement, registration and overlay measurement were verified.
The 2010 Symposia on VLSI Technology and Circuits will feature technology experts from SEMATECH. The event will take June 15-18 at the Hilton Hawaiian Village in Honolulu, Hawaii. SEMATECH will discuss the power and performance features that are critical to implementing next-generation devices, based on leading-edge research in areas such as logic and memory technologies, high-k/metal gate (HKMG) materials, and non-planar and planar CMOS technologies including exciting new high mobility channels and finFET designs.
SEMATECH’s Surface Preparation and Cleaning Conference (SPCC) will feature advanced technologies for cleaning, measuring and processing new III-V semiconductor materials for volume wafer manufacturing. SPCC 2010 will focus on particle removal, including next-generation materials, controlling processes to minimize impact on fragile device structures, non-damaging methods to remove resist, and new metrology approaches for measuring passivation and surface defects. SPCC will take place March 22-24, 2010 at the Sheraton Austin Hotel.
At SPIE Advanced Lithography 2010, SEMATECH will discuss issues and solutions in preparing extreme ultraviolet lithography (EUVL) for high-volume manufacturing. The SPIE Advanced Lithography conference will take place February 21-25 in San Jose, CA. SEMATECH will show how they are enabling EUV mask and resist/materials infrastructure as well as EUVL manufacturing feasibility and affordability. The SEMATECH Lithography Program is based at the College of Nanoscale Science and Engineering’s (CNSE) Albany NanoTech Complex.
The 2010 SEMATECH Knowledge Series (SKS) conferences will focus on difficult questions in lithography, advanced technologies, manufacturing, and strategy. Included are a new set of meetings on installed-base equipment utilization, and a new interconnect workshop in stress management for 3D chips utilizing through-silicon vias (TSVs). All SKS meetings are open to the public.
The SEMATECH-led workshop, Emerging Technologies in Solid State Devices, will take place December 5-6, 2009. Technologists, executives, and faculty from across the semiconductor R&D community will present technical data revealing advances in emerging memory technologies, energy efficient devices, and high mobility channel transistors. The SEMATECH workshop will feature over 40 presentations and panel discussions on cutting-edge solutions to the technical and manufacturing challenges associated with emerging nanoelectronics technologies.
At the IEEE International Electron Devices Meeting (IEDM), engineers from SEMATECH’s Front End Processes (FEP) program will present technical papers revealing research breakthroughs. SEMATECH experts will report on low defect density high-k gate stacks for alternative III-V channel materials and non-planar devices, and discuss a new dry etch approach to minimize etch related leakage — a significant process technology advancement for next-generation logic and memory technologies. The IEDM Conference will take place December 7-9, 2009, at the Hilton in Baltimore, MD.