Synopsys introduced the DesignWare DDR multiPHY. The IP solutions are mixed-signal PHY IP Cores that supply the complete physical interface to JEDEC standard DDR3, DDR3L (1.35V DDR3), DDR3U (1.2xV DDR3), DDR2, Mobile DDR and LPDDR2 SDRAM Memories up to 1066Mbps data rates. Synopsys DesignWare DDR multiPHY IP solutions are designed to support a broad range of DDR SDRAM standards in a single PHY without sacrificing power consumption or silicon area. The DesignWare DDR multiPHY is available now.
Jasper Design Automation rolled out Proof Kits for LPDDR1 and LPDDR2, and DDR3 SDRAM. The new LPDDR and DDR3 Proof Kits both speed verification for these high-demand memories, and ensure conformance with industry standards. The new DDR Proof Kits are currently available as a chapter within Jasper Formal Testplanner, and provided at no additional charge to current licensees of Formal Testplanner.