Tag Archives: Samsung Electronics

Cadence Design Systems, Samsung Electronics Team on 20nm Design Methodology

Cadence Design Systems and Samsung Electronics teamed together on a 20-nanometer design methodology. Their 20nm digital design methodology features double patterning technology for joint customer deployment and internal test chips. The new design methodology enables design at 20 nanometers and future process nodes. It is ideal for mobile consumer electronics.

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2011 Common Platform Technology Forum

The 2011 Common Platform Technology Forum will take place at the Santa Clara Convention Center on January 18th. The forum will present technical details of the 28nm HKMG design for low-power applications. The event will also include technology advancements in SoC enablement solutions, materials science, process technology and manufacturing. The Common Platform alliance was formed by IBM, Samsung Electronics and GLOBALFOUNDRIES. The alliance focuses on jointly developed digital CMOS process technologies and advanced manufacturing.

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Vertically Optimized 32/28nm Solution for Mobile SoC Design

Synopsys will take part in a technical session and breakfast at ARM TechCon3. ARM, the Common Platform (IBM, Chartered Semiconductor Manufacturing ,and Samsung Electronics) alliance, and Synopsys will discuss the new level of collaboration necessary to address the cost and technical challenges associated with advanced mobile SoC design and manufacturing. The event will take place Wednesday, October 21st, 8:30am – 10:30am at the Santa Clara Convention Center (Ballroom H).

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