Atrenta launched SpyGlass-Physical tool for early implementation analysis. SpyGlass-Physical provides early estimates of area, power, timing and routability for RTL designers without the need for physical design expertise or tools. The tool helps to achieve performance targets in concurrent block/SoC development processes by using interactive implementation analysis features. The result is enhanced guidance for the actual implementation of both IPs and full-chip SoCs. SpyGlass-Physical is currently in limited deployment.
Real Intent announced Meridian DFT for improving electronic design quality. Meridian DFT indentifies trouble spots during RTL creation. Meridian DFT checks the pre- and post-synthesis RTL for testability and DFT-related implementation errors. Meridian DFT will be available in Q3 2010.
Synopsys introduced Design Compiler 2010. The tool enables RTL designers to perform floorplan exploration within the synthesis environment to efficiently achieve an optimal floorplan. Design Compiler’s new scalable infrastructure tuned for multicore processors results in 2X faster synthesis runtimes on four cores. Design Compiler 2010 reduces iterations and run times in physical implementation.
Forte Design Systems released the latest version of CellMath Designer datapath synthesis and Cellmath IP software. The CellMath family enables register transfer level (RTL) designers to reduce area, improve performance and lower power consumption for their existing datapath-intensive design blocks. U.S. pricing starts at $120,000 for a one-year, time-based license.
OneSpin Solutions’ 360 MV formal assertion-based verification (ABV) solution has been integrated with Platform Computing’s LSF infrastructure. The customizable integration between 360 MV and Platform LSF enables engineers to adapt job scheduling and resource utilization to their needs. Designers can track named proof tasks using LSF monitoring tools, which report progress directly into the 360 MV graphical environment.
Averant introduced Solidify 5.2. The latest version of Solidify features accelerated analysis with multi-core computers, new Auto Check technology, and enhanced sequential equivalency checking (SEC). Release 5.2 is available immediately. Averant is a leader in property verification of RTL designs for digital integrated circuits.
Calypto Design Systems introduced a new PowerAdviser Flow. The new flow enables designers to deliver power-optimized SoC designs. Using sequential design information generated by Calypto’s PowerPro CG and PowerPro MG tools, the PowerAdviser Flow provides users with specific design changes that can be manually implemented in their RTL code to reduce power.
Real Intent launched Ascent Lint Version 1.2 for early functional verification. Ascent Lint v1.2 performs syntax and semantic Lint checks for complex SoC designs. Ascent Lint now offers rules from STARC Policy, Verilog and SystemVerilog Gotchas, Reuse Methodology Manual (RMM), Principles of Verifiable RTL Designs, and rules based on Real Intent industry expertise.
Synfora is oferring an on-demand webinar that describes the Fundamentals of ESL Synthesis. The webcast will provide RTL designers, systems engineers, and design managers with technical insight into the benefits of high level synthesis, how it operates, and the kinds of transformations that can be made. The online course is presented by Brian Bailey, who is an independent consultant working in the areas of functional verification and ESL. He provides methodology guidance and technical insights to both the EDA industry and the systems industry.
Bernard Murphy, Chief Technology Officer of Atrenta, will present a paper at ARM techcon3 (formerly ARM Developers Conference) from 10:00 to 10:45 am on Friday, October 23, 2009. The title of the paper is A Power Backbone for architecture to RTL power efficient SoC Design. Dr. Murphy’s paper describes a real-world implementation of such an RTL-based design flow.