OneSpin Solutions launched 360 EC-RTL equivalence checking software. OneSpin’s 360 EC-RTL compares revisions of register transfer level (RTL) code. 360 EC-RTL is part of the OneSpin 360 EC Product Family. It is a RTL-to-RTL equivalence checker used to exhaustively compare two revisions of synthesizable RTL code. The software features robust register, sequential and power optimization verification. 360 EC-RTL is shipping now.
Cadence Design Systems launched the Incisive Debug Analyzer. The new tool is a verification debug solution for RTL, testbench and SoC verification. It helps designers reduce debug time and effort. The Incisive Debug Analyzer integrates seamlessly into existing Incisive debug flows, fully leveraging SimVision for waveform and transaction-level debug. The tool will be released at the end of the year.
Synopsys and Semiconductor Manufacturing International Corporation (SMIC) released version 5.0 of their 40-nanometer RTL-to-GDSII reference design flow. The SMIC-Synopsys Reference Flow 5.0 enables IC designers to accelerate their designs into manufacturing through the combination of SMIC’s 40nm process technology and Synopsys’ technology-leading design solutions. The SMIC-Synopsys Reference Flow 5.0 is available now.
SynaptiCAD rolled out a new version of their Verilog2VHDL tool. The SynaptiCAD V2V tools translate bidirectionally between Verilog and VHDL source code. The translators are are ideal for converting behavioral and/or RTL-level code to a preferred design language. The V2V translation software is available on Windows and Linux. The SynaptiCAD software can be licensed on either a permanent or leased basis, and both floating and node-locked versions are available.
ANSYS introduced RTL Power Model (RPM). Their technology helps engineers optimize a wide range of power-sensitive applications. It bridges the power gap from register transfer language (RTL) design to physical implementation. RPM accurately predicts integrated circuit (IC) power behavior at the RTL level with consideration for how the design is physically implemented. RTL Power Model enables chip power delivery network (PDN) and IC package design decisions early in the design process.
OneSpin Solutions introduced Quantify MDV, which is an enhancement to the OneSpin 360 MV product family. The Quantify MDV formal metric-driven verification (MDV) solution automatically analyzes and measures formal verification progress and quality in register transfer level (RTL) designs. Quantify MDV is available now as part of the standard 360 MV product line, which starts at $25,000 for a one-year time-based license.
Atrenta launched version 4.5 of their SpyGlass product family. SpyGlass 4.5 features improvements in usability, debug, advanced linting, power estimation and reduction, CDC verification, constraints management, and testability. SpyGlass v4.5 is now in production and available for download. Atrenta’s SpyGlass solution methodology provides a structured, easy to use and a comprehensive method for solving RTL design issues.
SynaptiCAD rolled out a new verion of TestBencher Pro, which is a VHDL and Verilog system-level testbench generation software. The tool simplifies the process of creating and applying random bus transactions to RTL and gate-level models. The latest version of TestBencher Pro simplifies the creation of testbenches that reside in a different compiled library from the design being tested.
Calypto Design Systems rolled out version 4.1 of PowerPro, which is an advanced RTL power optimization product family. Calypto’s PowerPro 4.1 runs on PC platforms running Linux. PowerPro CG and PowerPro MG are each priced at $295K for a one-year, time-based license. PowerPro Analyzer is included with either PowerPro CG or PowerPro MG.
Aldec introduced Riviera-PRO 2010.06 RTL and gate-level simulator. Riviera-PRO 2010.06 supports the Open Verification Methodology (OVM) co-authored by Cadence (NASDAQ:CDNS) and the early release of the Universal Verification Methodology (UVM) from Accellera. OVM and UVM provide common building blocks and predefined mechanisms for building reusable and expandable test environments that take full advantage of SystemVerilog verification capabilities. Riviera-PRO 2010.06 verification platform is available now.